Test Boards Design for LTDB - PowerPoint Presentation

Slide1

Test Boards Design for LTDB

Xueye

Hu,

Hucheng

Chen, Joe Mead

USTC & BNL

06/20/2012

2

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card

FPGA Carrier Card

Test

Conclusion

3

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card

FPGA Carrier Card

Test

Conclusion

LTDB Test Boards

LTDB:

Phase 1 Upgrade of LAr Front- End electronics

Setup irradiation test (Proton beam)

LTDB Test boards:

Three Steps

Step 2

Modular design

verify the functionalities

1

：

ADC Mezzanine Card

2: FPGA Carrier Card

Step 1

3: Optical Mezzanine Card (SMU)

5

Re-integrate into ¼slice LTDB Digital Mezzanine Card & A LTDB MOTHER Board

Step 3

Function of FPGA Carrier Card

Function of ADC Mezzanine Card

Function of Optical Mezzanine Card

LTDB Digital Mezzanine Card

L

iquid Argon

T

rigger

D

igitizer

B

oard

MOTHER Board

Analog

Interface

Analog Mezzanine card

6

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card FPGA Carrier Card Test Conclusion

7

Key

Features

Input: SMA

connectors

Output: FMC HPC

connector

ADC

Mezzanine Card

ADC Sampling clock: SMA / OSC/ FPGA differential output

ADC reference: internal / external

Hardware

ADC Driver: AD8138 /500krad

Clock Driver: CDC1212 /1Mrad

Power supply: external supply || on board POL converter

*3

SMA

POWER CONNECTORPOL CONVERTERADC

OSCFMC CONNECTORASP-134602-01SMASMA

...CLK Driver

ADC DRIVERBlock Diagram of ADC Test Boards

8

First ADC test board using TI ADS5263

ADS5263

: 4-ch,

16bit/14bit,

100MSPS

Board has been

assembled

Second ADC test board using TI ADS5294

ADS5294

: 8-ch, 14bit, 80MSPS

B

oard has been assembled

Third ADC test board using TI ADS5272ADS5272: 8-ch, 12bit, 65MSPSSurvived more than 8Mrad so farSimple architecture and small (6.5 clock cycle) latencyPCB design is ongoingADC

ADC @Test Boards

TI ADS5263 Test Board

TI ADS5294 Test Board

For irradiation test

Clearance circle with 3inch diameter

10

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card FPGA Carrier Card Test Conclusion

11

FMC CONNECTOR

ASP-134602-01

OSC

S

XILINX Kintex-7

XC7K325T

POWER CONNECTOR

POL CONVERTER

LDO Regulators

FMC CONNECTOR

ASP-134602-01

Diff. pairs

Single ended

USB

USB-UARTBridgeFlashDDR3SO-DIMM

12*10Gbps

SMA

sSFPADC DATAGTX DATACurrent

MonitorBlock Diagram of FPGA Test Board FPGA Carrier CardJTAG

12

Key

Features

Hardware

FPGA

Carrier Card

FMC HPC connectors

receive ADC differential data & transmit 10Gbps serial data

Memory: DDR3

Ethernet interface: SFP cage & RJ45

RS232 port:

Mini-USB & SiLabs CP2103

Configuration: BPI flash & JTAG

FPGA: XC7K325T-1FFG900 XADC: monitoring temperature and voltage

Power: POL converter LTM4616

LTM4616 & Diode FDLL4148: FPGA power-on sequenceClock: ADC Mezzanine card & differential oscillatorSMA: test GTX electrically

For irradiation test

Clearance circle with 2.5inch diameter

FPGA @Test Board

14

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card FPGA Carrier Card Test Conclusion

15

Setup of Test

Preparation

Make our ADC test

boards

more generic ML605, KC705, FPGA Carrier card

A mapping spreadsheet:

Define the FMC HPC connector signals

carefully

Two FPGA banks transfer differential signals

two pairs for clock signals, up to 16 pairs for ADC DATA signals

Third FPGA bank for ADC single ended signal

Preparation

ADC preliminary test Verify ADC functionalities FPGA preliminary test

16

FPGA

ML605

Board

ADC

Board

Setup of Test

Ongoing test

ADS5263

ADS5294

FPGA Carrier card

ADC preliminary test

ADS5263: power supply, OSC, ADC Driver, Clock Driver work well

ADS5294: work well

*

DCLK, FCLK are not stable with missing cycles It turns out that the analog supply voltage threshold is 1.84V Adjust DC/DC Converters output voltage

17

Setup of Test

Verify ADC functionalities

(VHDL code on ML605)

ADC interface (S2P) : ADC serial LVDS output parallel data in FPGA

Control (SPI): control ADC serial register & configure ADC

ChipScope: capture the S2P and SPI data directly from FPGA hardware

ADS5263 configuration: 2-wire, 16x serialization, 4 x bit clock, 1 x frame clock, Bytewise mode

ADC Sampling clock = 40MHz, FCLK= 40MHz, DCLK= 160MHz

Configure ADC and sample ADC data properly

ADC

Sampling

clock = 80MHz, FCLK= 80MHz, DCLK= 320MHz

* add clock adjustment module OKADS5294 configuration: 2-wire, 14x serialization, 4 x bit clock, 1 x frame clock, Wordwise modeSPI works fine & S2P debugging is ongoing

18

FPGA preliminary test

@ power

supply

works

well & power-on sequence has verified with ADM chip and FDLL4148

@ Kintex-7 FPGA is tested with a small LED blinking program JTAG configuration & power on sequence work properly

@ MicroBlaze system built on FPGA carried card

*

DDR3 memory & USB--UART work well

Data rate DDR3: 64 bit * 100MHz = 6.4

Gbps ADS5263: 4ch * 16bit * 80MHz = 5.12Gbps ---- DDR3 can handle ADC data input easily * Gigabit Ethernet test is ongoing

Setup of Test

19

Outline

LTDB Test Boards

L

Ar

T

rigger

D

igitizer

B

oard

ADC Mezzanine Card FPGA Carrier Card Test Conclusion

Conclusion

1.1: Two ADC

(ADS2563, ADS5294)

mezzanine cards

(

Done

)

1.2: FPGA carrier card

(

Done

)

1.3: The third ADC

(ADS5272)

layout

(Ongoing)

2.1: ADC

(ADS5263)

mezzanine card function test (Done)

2.2: ADC (ADS5294) mezzanine card function test (Ongoing)

2.3: ADC Irradiation Test S2P & SPI integrated on ML605 MicroBlaze system (Ongoing)

21

Thank you !