/
REV A Information furnished by Analog Devices is believed to be accurate and reliable REV A Information furnished by Analog Devices is believed to be accurate and reliable

REV A Information furnished by Analog Devices is believed to be accurate and reliable - PDF document

alida-meadow
alida-meadow . @alida-meadow
Follow
469 views
Uploaded On 2014-12-14

REV A Information furnished by Analog Devices is believed to be accurate and reliable - PPT Presentation

A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third part ID: 23657

Information furnished

Share:

Link:

Embed:

Download Presentation from below link

Download Pdf The PPT/PDF document "REV A Information furnished by Analog De..." is the property of its rightful owner. Permission is granted to download and print the materials on this web site for personal, non-commercial use only, and to display it on your personal computer provided you do not modify the materials and that you retain all copyright notices contained in the materials. By downloading content from our website, you accept the terms of this agreement.


Presentation Transcript

REV.A Fax: 781/326-8703© Analog Devices, Inc., 2002 MFLTVIDEO OUTPUT Ð AINPAOFSACOMMOFSBINPBVPOS +Ð +Ð 60dB LOG AMPS(7 DETECTORS) 60dB LOG AMPS(7 DETECTORS)VIDEO OUTPUT Ð BPHASEDETECTOR +Ð BIAS x31.8V AD8302 system, AD8302ÐSPECIFICATIONS ParameterConditionsMinTypMaxUnitInput Frequency Range�02700MHzGain Measurement RangeP30dB90Degree Reference Voltage OutputPin VREF, Ð40C1.721.81.88VINPUT INTERFACEPins INPA and INPBInput Simplified Equivalent CircuitTo AC Ground, f 500 MHz3Input Voltage RangeAC-Coupled (0 dBV = 1 V rms)Ð73Ð13dBVÐ600dBmCenter of Input Dynamic RangeÐ43dBV Ð30dBmMAGNITUDE OUTPUTPin VMAGOutput Voltage Minimum20 ) = Ð30 dB30mVOutput Voltage Maximum20 ) = +30 dB1.8VCenter Point of Output (MCP)V = V900mVOutput CurrentSource/Sink8mASmall Signal Envelope BandwidthPin MFLT Open30MHzSlew Rate40 dB Change, Load 20 pF25V/Rise TimeAny 20 dB Change, 10%Ð90%50nsFall TimeAny 20 dB Change, 90%Ð10%60ns Settling TimeFull-Scale 60 dB Change, to 1% Settling300nsPHASE OUTPUTPin VPHSOutput Voltage MinimumPhase Difference 180 Degrees30mVOutput Voltage MaximumPhase Difference 0 Degrees1.8VPhase Center PointWhen 900mVOutput Current DriveSource/Sink8mASlew Rate25V/30MHzResponse TimeAny 15 Degree Change, 10%Ð90%40ns =1 pF, to 1% Settling500ns100 MHzMAGNITUDE OUTPUT = Ð43 dBV)58dB = Ð30 dBm (V = Ð43 dBV)55dB = Ð30 dBm (V = Ð43 dBV)42dBSlopeFrom Linear Regression29mV/dBDeviation vs. TemperatureDeviation from Output at 25 = Ð30 dBm0.25dBDeviation from Best Fit Curve at 25 = Ð30 dBm0.25dB Gain Measurement BalanceP= Ð5 dBm to Ð50 dBm0.2dBDynamic RangeLess than 1 Degree Deviation from Best Fit Line145DegreeLess than 10% Deviation in Instantaneous Slope143DegreeSlope (Absolute Value)From Linear Regression about Ð90 or +9010mV/DegreeDeviation vs. TemperatureDeviation from Output at 25C, Delta Phase = 90 Degrees0.7DegreeDeviation from Best Fit Curve at 25 30 Degrees0.7Degree REV. AÐ3Ð ParameterConditionsMinTypMaxUnit900 MHzMAGNITUDE OUTPUT = Ð43 dBV)58dB = Ð30 dBm (V = Ð43 dBV)54dB = Ð30 dBm (V = Ð43 dBV)42dBSlopeFrom Linear Regression28.7mV/dBDeviation vs. TemperatureDeviation from Output at 25 = Ð30 dBm0.25dBDeviation from Best Fit Curve at 25 = Ð30 dBm0.25dB Gain Measurement BalanceP= Ð5 dBm to Ð50 dBm0.2dBDynamic RangeLess than 1 Degree Deviation from Best Fit Line143DegreeLess than 10% Deviation in Instantaneous Slope143DegreeSlope (Absolute Value)From Linear Regression about Ð90 or +9010.1mV/DegreeDeviationLinear Deviation from Best Fit Curve at 25C, Delta Phase = 90 Degrees0.75Degree30 Degrees0.75Degree Phase Measurement BalancePhase @ INPA = Phase @ INPB, P = Ð5 dBm to Ð50 dBm0.81900 MHzMAGNITUDE OUTPUT = Ð43 dBV)57dB = Ð30 dBm (V = Ð43 dBV)54dB = Ð30 dBm (V = Ð43 dBV)42dBSlopeFrom Linear Regression27.5mV/dBDeviation vs. TemperatureDeviation from Output at 25 = Ð30 dBm0.27dBDeviation from Best Fit Curve at 250.33dB Gain Measurement BalanceP= Ð5 dBm to Ð50 dBm0.2dBDynamic RangeLess than 1 Degree Deviation from Best Fit Line128DegreeLess than 10% Deviation in Instantaneous Slope120DegreeSlope (Absolute Value)From Linear Regression about Ð90 or +9010.2mV/DegreeDeviationLinear Deviation from Best Fit Curve at 25C, Delta Phase = 90 Degrees0.8Degree30 Degrees0.8Degree = Ð5 dBm to Ð50 dBm1Degree2200 MHzMAGNITUDE OUTPUT = Ð43 dBV)53dB = Ð30 dBm (V = Ð43 dBV)51dB = Ð30 dBm (V = Ð43 dBV)38dBSlopeFrom Linear Regression27.5mV/dBDeviation vs. TemperatureDeviation from Output at 25 = Ð30 dBm0.28dBDeviation from Best Fit Curve at 25 = Ð30 dBm0.4dB Gain Measurement BalanceP= Ð5 dBm to Ð50 dBm0.2dBDynamic RangeLess than 1 Degree Deviation from Best Fit Line115DegreeLess than 10% Deviation in Instantaneous Slope110DegreeSlope (Absolute Value)From Linear Regression about Ð90 or +9010mV/DegreeDeviationLinear Deviation from Best Fit Curve at 25C, Delta Phase = 90 Degrees0.85Degree 30 Degrees0.9DegreeREFERENCE VOLTAGEPin VREFOutput VoltageLoad = 2 k1.71.81.9VPSRRV = 2.7 V to 5.5 V0.25mV/V Output CurrentSource/Sink (Less than 1% Change)5mAPOWER SUPPLYPin VPOS2.75.05.5VOperating Current (Quiescent)V = 5 V1925mA C2127mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VPSET, MSET Voltage . . . . . . . . . . . . . . . . . . . . . .V + 0.3 VINPA, INPB Maximum Input . . . . . . . . . . . . . . . . . . Ð3 dBV . . . . . . . . . . . . . . . . . . 10 dBm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Maximum Junction Temperature . . . . . . . . . . . . . . . . 125Operating Temperature Range . . . . . . . . . . . Ð40Storage Temperature Range . . . . . . . . . . . . Ð65Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300 TOP VIEW(Not to Scale) AD8302INPACOMM313 PIN FUNCTION DESCRIPTIONS Equivalent Pin No.MnemonicFunctionCircuit1, 7COMMDevice Common. Connect to low impedance ground.2INPAHigh Input Impedance to Channel A. Must be ac-coupled.Circuit A3OFSAA capacitor to ground at this pin sets the offset compensation filter cornerCircuit A4VPOSVoltage Supply (V5OFSBA capacitor to ground at this pin sets the offset compensation filter cornerCircuit A6INPBInput to Channel B. Same structure as INPA.Circuit A8PFLTLow Pass Filter Terminal for the Phase OutputCircuit E9VPHSSingle-Ended Output Proportional to the Phase Difference between INPACircuit B10PSETFeedback Pin for Scaling of VPHS Output Voltage in Measurement Mode.Circuit D11VREFInternally Generated Reference Voltage (1.8 V Nominal)Circuit C12MSETFeedback Pin for Scaling of VMAG Output Voltage Measurement Mode.Circuit D13VMAGSingle-Ended Output. Output voltage proportional to the decibel ratioof signals applied to INPA and INPB.Circuit B 14MFLTLow Pass Filter Terminal for the Magnitude OutputCircuit E ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD8302 features proprietary ESD protection circuitry, permanent damage may occur on recommended to avoid performance degradation or loss of functionality. WARNING!ESD SENSITIVE DEVICE ORDERING GUIDE Package Model Temperature RangePackage DescriptionOptionAD8302ARUÐ40CTube, 14-Lead TSSOPRU-14AD8302ARU-REEL13" Tape and ReelAD8302ARU-REEL77" Tape and Reel AD8302-EVALEvaluation Board REV. A AD8302 OFSA(OFSB)VPOSON TOLOG-AMPÐ   Figure 1.Equivalent Circuits (VPHS) CLASS A-BCONTROL  Circuit B VPOS 5k Circuit C VPOS (PSET) ACTIVE LOADS10k10k Circuit D (PFLT) 1.5pF Circuit E Typical Performance Characteristics MAGNITUDE RATIO VMAG 5051015202530 TPC 1.Magnitude Output (VMAG)(Gain) V1900 MHz, 2200 MHz, 2700 MHz, 25 MAGNITUDE RATIO VMAG 5051015202530 TPC 2.VMAG vs. Input Level Ratio (Gain) V MAGNITUDE RATIO VMAG 100102030 ERROR IN VMAG 1.50 40C+25C+85C TPC 3.VMAG Output and Log Conformance vs. Inputand +85 MAGNITUDE RATIO VMAG 100102030 ERROR IN VMAG 1.50 C C 40C TPC 4.VMAG and Log Conformance vs. Input Level RatioC, and +85 MAGNITUDE RATIO VMAG 100102030 ERROR IN VMAG 1.35 C 40C+25C TPC 5.VMAG and Log Conformance vs. Input Level Ratio MAGNITUDE RATIO VMAG 100102030 ERROR IN VMAG 1.6501.501.35 C C 40C TPC 6.VMAG Output and Log Conformance vs. InputLevel RC, +25and +85 REV. A AD83027Ð MAGNITUDE RATIO ERROR IN VMAG 5051015202530 40 40 TPC 7.Distribution of Magnitude Error vs. Input LevelC, +25 MAGNITUDE RATIO ERROR IN VMAG 5051015202530 40 40 TPC 8.Distribution of Error vs. Input Level Ratio (Gain),C, +25 MAGNITUDE RATIO ERROR IN VMAG 5051015202530 40 40 TPC 9.Distribution of Magnitude Error vs. Input Level MAGNITUDE RATIO VMAG 5051015202530 TPC 10.Distribution of VMAG vs. Input Level Ratio (Gain),C and +85 MAGNITUDE RATIO VMAG 100102030 45dBm ERROR IN VMAG 30dBm 45dBm 30dBm 15dBm 15dBm TPC 11.VMAG Output and Log Conformance vs. Input VMAG INPA INPAINPB INPAINPB TPC 12.VMAG 5 dB, Frequency 1900 MHz REV. AAD83028Ð FREQUENCY VMAG 2004006008001000120014001600180020002200 INPAINPA INPA TPC 13.VMAG Output vs. Frequency, for P = P TEMPERATURE 20020406080 TPC 14.Change in VMAG Slope vs. Temperature, Three TEMPERATURE VMAG 100102030405060708090 TPC 15.Change in Center Point of Magnitude Output 0.800.850.90 TPC 16.Center Point of Magnitude Output (MCP) 27.027.528.028.529.530.0 VMAG SLOPE TPC 17.VMAG Slope, Frequency 900 MHz, 17,000 Units FREQUENCY SLOPE OF VMAG 4001000 TPC 18.VMAG Slope vs. Frequency REV. A AD83029Ð HORIZONTAL VERTICAL TPC 19.Magnitude Output Response to 4 dB Step, for HORIZONTAL VERTICAL TPC 20.Magnitude Output Response to 4 dB Step, for HORIZONTAL VERTICAL TPC 21.Magnitude Output Response to 40 dB Step, for FREQUENCY VMAG 1k10k100k1M10M 100M100010010 50dBm 30dBm10dBm TPC 22.Magnitude Output Noise Spectral FREQUENCY VMAG 1k10k100k1M10M100M 50dBm 30dBm10dBm TPC 23.Magnitude Output Noise Spectral Density, P = P50 dBm, with Filter Capacitor, C = 1 nF MAGNITUDE RATIO VMAG (PEAK-TO-PEAK) 1025505101520 0.160.14 900190022002700 TPC 24.VMAGFrequencies 100 MHz, 900 MHz, 1900 MHz, 2200 MHz, and REV. AAD8302 202060100140180 TPC 25.Phase Output (VPHS) vs. Input Phase Difference, 300306090120150180ERROR TPC 26.VPHS Output and Nonlinearity vs. Input Phase 300306090120150180ERROR TPC 27.VPHS Output and Nonlinearity vs. Input Phase 300306090120150180ERROR TPC 28.VPHS Output and Nonlinearity vs. Input Phase 300306090120150180ERROR TPC 29.VPHS Output and Nonlinearity vs. Input Phase ERROR 300306090120150180 40C+85C+25C TPC 30.Distribution of VPHS Error vs. Input Phase Differ-C, +25 REV. A AD8302 ERROR 300306090120150180 40C+85C+25C TPC 31.Distribution of VPHS Error vs. Input Phase ERROR 300306090120150180 40C+85C+25C TPC 32.Distribution of VPHS Error vs. Input Phase Differ- V300306090120150180 TPC 33.Distribution of VPHS vs. Input Phase Differ-C and +85 TEMPERATURE 1001020304050608090 Ð0.30Ð0.25Ð0.20Ð0.15Ð0.10Ð0.050.00 MEAN +3 SIGMA MEAN 3 SIGMA TPC 34.Change in VPHS Slope vs. Temperature, Three 1001020304050608090 +3 SIGMA Ð3 SIGMA 70Ð35Ð30Ð25Ð20Ð15Ð10Ð5010 TPC 35.Change in Phase Center Point (PCP) vs.Frequency 1900MHz 0.750.800.850.900.951.001.05 TPC 36.Phase Center Point (PCP) Distribution, Frequency REV. AAD8302 9.59.79.910.110.310.510.710.9 TPC 37.VPHS Slope Distribution, Frequency 50ns HORIZONTALVERTICAL TPC 38.VPHS Output Response to 4 s HORIZONTALVERTICAL TPC 39.VPHS Output Response to 4Phase Shift of 90Supply 5 V, Frequency 1900 MHz, 25 50ns HORIZONTALVERTICAL TPC 40.VPHS Output Response to 40Phase Shift of 90 FREQUENCY 10k100k1M10M100M 30dBm10dBm TPC 41.VPHS INPA 300306090120150180 INPAINPAINPA TPC 42.Phase Output vs. Input Phase Difference, PINPB + 15 dB, P REV. A AD8302 ABSOLUTE VALUE OF VPHSINSTANTANEOUS SLOPE 300306090120150180 INPA INPAINPA TPC 43.Phase Output Instantaneous Slope, 300306090120150180 INPA INPAINPA TPC 44.Phase Output vs. Input Phase Difference, ABSOLUTE VALUE OF VPHSINSTANTANEOUS SLOPE 300306090120150180 INPAINPA INPA TPC 45.Phase Output Instantaneous Slope, P 300306090120150180 INPAINPAINPA 1.26 TPC 46.Phase Output vs. Input Phase Difference, 300306090120150180 INPAINPAINPA 8 ABSOLUTE VALUE OF VPHSINSTANTANEOUS SLOPE TPC 47.Phase Output Instantaneous Slope, P REAL SHUNT Z () FREQUENCY RESISTANCE 5001000150020002500 CAPACITANCE CAPACITANCE SHUNT Z (pF) TPC 48.Input Impedance, Modeled as Shunt R in Parallel REV. AAD8302 TEMPERATURE 1001020304050607090 TPC 49.Change in VREF vs. Temperature, Three Sigma to FREQUENCY 10k100k1M10M100M TPC 50.VREF Output Noise Spectral Density vs. 1812915 1.781.821.841.861.881.761.80 TPC 51.VREF Distribution, 17,000 Units REV. A ematical form is: VVVVOUTSLPINZlog/ is the input voltage, is called the intercept (voltage), is called the slope (voltage). It is assumed throughoutthat log(x) represents the log10(x) function. is thus thesignal that results in an output of zero and need not to a physically realizable part of the log amp variability introducesdifferent levels. Since subtraction in the logarithmic domain VVVVMAGSLPINAINBlog/ and are the input voltages, is the output is the slope. Note that the intercept, has droppedtechnique depends on the two log amps being well matchedin slope and intercept to ensure cancellation. for an integrated pair of log amps. N Theboth log amps drive an exclusive-OR style digital phase detector.Operating strictly on the relative zero-crossings of the limited nals, the extracted phase difference is independent of the original VVVVPHSINAINB is the phase slope in mV/degree and is each The general form of the AD8302 is shown in Figure 2. Theence voltage buffer. The log amps and phase detector processmation in current form to the output amplifiers. The output MFLTPSETVREFVIDEO OUTPUT Ð AVPOS Ð Ð 60dB LOG AMPS(7 DETECTORS) (7 DETECTORS)VIDEO OUTPUT Ð BDETECTOR Ð 1.8V Figure 2.General StructureEach log amp consists of a cascade of six 10 dB gain stages withSince there is a total of 60 dB of cascaded gain, slight dc offsets The nominal high-pass corner frequency, fcapacitance to the OFSA and OFSB pins. Signals at frequencies from dcputs is performed in the current domain, yielding by analogy to IIVVLASLPINAINBlog/ where and are the output current difference and theslope is derived from an accurate reference designed to be insen-to its two inputs to maintain balanced delays along both signalto common-mode perturbations. The current-mode equivalentto Equation 3 is: IIVVPDINAINB and are the output current and characteristic slopederived from the same reference as the log amp slope. to +180 phase difference range that can be either 0 to +180 centered or 0 to centered at VRIIsTOUTFINFB is the feedback current equal to ( is the integration time constant equal is the parallel combination of the inter- F CP 1.5pF FLT IN LA Figure 3.Simplified Block Diagram of the Output Interface VIRV/sTOUTINFCP represents the single-pole response to the enve- is used, the AD8302 can be added as necessary accord- (pF). For best transient response with COMMMFLT INPAVMAG213 OFSAMSET312 VPOSVREF411 OFSBPSET510 INPBVPHS COMMPFLT C4C6C5R1 V R4 Figure 4.Basic Connections in Measurement Mode with30 mV/dB and 10 mV/Degree Scaling VRIVVVorMAGFSLPINAINBCPlog/ VRIPPVMAGFSLPINAINBCP/20 VRIVVVPHSFINAINBCP and are at a specified refer- is 600 mV/decade or, dividing by 20 dB/decade, 30 mV/dB. is 10 mV/degree. With a to 180 covers the to covers 300+30 +10mV/DEG90090180 Figure 5.Idealized Transfer Characteristics for the Gain REV. A Each consists of a driving pin, INPA and INPB, and an ac-compensation loop. There is an internal 10 pF capacitor to ground (MHz) = is the total capacitance from OFSA or OFSBparasitics. At moderate frequencies above f resistor in parallel with a 2.2GHz2.7GHz3.0GHz 900MHz100MHz Figure 6.Smith Chart Showing the Input Impedance of acapacitors can be used to match to a given source i, is determined by: RRRRRTINSINS is the input resistance and the source impedance.At higher frequencies, a reactive, narrow-band match might bedesirable to tune out the reactive portion of the input impedance.An important attribute of the two-log-amp architecture is tboth channels are at the same frequency and have the same network, then impedance mismatches and reflection losses (V, Ð60 dBm re: 50 to Ð13 dBV (223 mV, 0 dBm re: 50 )]. Note that logamps respond to voltages and not power. An equivalent powercan be inferred given an impedance level, e.g., to convert fromdBV to dBm in a 50 system, simply add 13 dB. To cover30 dB below midrange, to its high end, 30 dB above midrange. Ifthe reference is displaced from midrange, some measurementFigure 7 illustrates the effect of the reference channel level place20 dB rather than 30 dB. If the reference GAIN MEASUREMENT RANGE Ð dB 30 0+30 MAX RANGE FOR VREF = VREF � VREF REF Figure 7.The Effect of Offsetting the Reference Level Is to to 180 to between the two input channels. At higher frequencies, the finiteambiguous situation that leads to inaccessible dead zones at the and 180 limits. For maximum phase difference coverage, thereference phase difference should be set to 90 outputs. Figure 8 demonstrates how a simple voltage dividerfrom the VMAG and VPHS pins to the MSET and PSET pinscan be used to modify the slope. The increase in slope is given by). Note that it may be necessary to account for which has a manufacturing tolerance. As is generally true in such feedbacksystems, envelope bandwidth is decreased and the output noisetransferred from the input is increased by the same factor. For and 20 krespectively, gain slope increases from the nominal 30 mV/dBof 2 and the new center point is at from = 0 V, to 0 dB, = 1.8 V. NEW SLOPE = 30mV/dB  1R1R2  R2 Figure 8.Increasing the Slope Requires the Inclusion of agrounded voltage may be provided externally or derived from the internalreference voltage on pin VREF. For the specific choice of R2 =The increase in slope is now simplified to 1 + R1/10k. Since thisshould be better in comparison to a fixed external voltage. If thecenter point is shifted to 0 dB in the previous example w = 0 V to 15 dB at V = 1.8 V. 10k NEW SLOPE = 30mV/dB   20k Figure 9.The Center Point Is Repositioned with the Helpthe arrangement shown in Figure 10 where the DUT is the elementconnected to MSET and PSET. The trip-point thresholds for thevoltages applied to pins MSET and PSET according to: VVmVdBGaindBmV()() 30900 VVmVPhasemV()|()| 1090900 ) are the desired gain andphase thresholds. If the actual gain and phase between the twoinput channels differ from these thresholds, the V and V VifGainGainVifGainGain VifPhasePhaseVifPhasePhase COMMMFLT INPAVMAG213 OFSAMSET312 VPOSVREF411 OFSBPSET510 INPBVPHS COMMPFLT C4C6C5R1 V R4 Figure 10.Disconnecting the Feedback to the Setpoint REV. A closing the loop around the VMAG and VPHS outputs.If VMAG and VPHS are properly conditioned to drive gain andAGC and APC loops. Note that as with all control loops of this kind, MAGSETPOINTPHASESETPOINTVMAGPSETINPAINPB Figure 11.By Applying Overall Feedback to a DUT Viaof the gain and phase response of a functional circuit block such asan amplifier or a mixer. As illustrated in Figure 12, directional and DC DUT. The attenuators ensure that the signalFrom the discussion in the Dynamic Range section, the optimal = 30 dBm referenced to 50 43 dBV. To achieve this, the combination CLPPBBINOPT and are the coupling coefficients, and are the is the nominal DUT gain. Iftwo attenuators compensates for the nominal DUT gain. When theactual gain is nominal, the VMAG output is 900 mV, corresponding900 mV or 0 dB with a 30 mV/dB scaling. Depending on phase measurement mayrequire a fixed phase shift in series with one of the channels to point.When the insertion phase is nominal, the VPHS output is 900 mV.ions from the nominal are reported with a 10 mV/degreescaling. measurement of an amplifier with a nominal gain of 10 dB and ATTEN A B BLACK BOXÓ COMMMFLT INPAVMAG213 OFSAMSET312 VPOSVREF411 OFSBPSET510 INPBVPHS COMMPFLT C4C6C5R1 R4 Figure 12.Using the AD8302 to Measure the Gain andTable I.Component Values for Measuring a 10 dB Amplifier ComponentValueQuantityR1, R252.3 R5, R6100 C1, C4, C5, C60.001 C2, C8OpenC3100 pF1C70.1 AttenA10 dB (See Text)1AttenB1 dB (See Text)1 20 dB2The gain measurement application can also monitor gain andphase distortion in the form of AM-AM (gain compression) andcorresponds to those at low input signal levels. As the input levellevels over which the input is swept must remain within the dynamic CLPGAINPAAINNOMOPT  REV. AAD8302The AD8302 can be configured to measure the magnitude ratioand phase difference of signals that are incident on and reflectedfrom a load. The vector reflection coefficient, , is defined as,  flectedVoltage/IncidentVoltageZZ/ZZLOLO is the complex load impedance and is the charac-teristic system impedance.level of impedance mismatch or standing wave ratio (SWR) of areflectomcoupling coefficients CLPPBBINOPT CLPPAAINNOMOPT  is the nominal reflection coefficient in dB and is19 dB.As shown in Figure 13, using 20 dB couplers on both sides andare 1 dB and 20 dB, respectively. The magnitude and phase ofpins scaled to 30 mV/dB and 10 mV/degree. When is . Keep the paths from the couplersintroduce measurement errors. The finite directivity, D, of thecouplers sets the minimum detectable reflection coefficient, i.e., (dB)|() C4C6C5 R4 COMMMFLT INPAVMAG213 OFSAMSET312 VPOSVREF411 OFSBPSET510 INPBVPHS COMMPFLT Figure 13.Using the AD8302 to Measure the Vector REV. A Table III.Evaluation Board Configuration Options ComponentFunctionP1Power Supply and Ground Connector: Pin 2 VPOS and Pins 1 and 3 Ground.Not ApplicableR1, R2Input Termination. Provide termination for input sources.R1 = R2 = 52.3 (Size 0402)R3VREF Output Load. This load is optional and is meant to allow the user to simulateR3 = 1 k (Size 0603)R5, R6, R9Snubbing ResistorR5 = R6 = 0 (Size 0603) (Size 0603)C3, C7, R4Supply DecouplingC3 = 100 pF (Size 0603)C7 = 0.1 (Size 0603)C1, C5Input AC-Coupling CapacitorsC1 = C5 = 1 nF (Size 0603)C2, C8Video Filtering. C2 and C8 limit the video bandwidth of the gain and phaseC2 = C8 = Open (Size 0603)C4, C6Offset Feedback. These set the high-pass corner of the offset cancellation loopand thus with the input ac-coupling capacitors the minimum operating frequency.C4 = C6 = 1 nF (Size 0603)SW1GSET Signal Source. When SW1 is in the position shown, the device is in gainSW1 = InstalledSW2PSET Signal Source. When SW2 is in the position shown, the device is in phaseSW1 = Installed must be applied to PSET. Figure 15a.Component Side Metal of Evaluation Board Figure 15b.Component Side Silkscreen of Evaluation Board Table II.P1 Pin Allocations1Common2VPOS 3Common C4C6C5 R2 Figure 14.Evaluation Board Schematic The general hardware configuration used for most of the AD8302characterization is shown in Figure 16. The characterization both a TDS 744A oscilloscope with 10 high impedanceand Agilent 34401A multimeters.with the DMM. In practice, the two sources were run at 100 kHzAlpha AD260, is driven with a HP8112A pulse generator pro- phase splitter.To measure the modulation of VMAG due to phase variation seconds. The VMAG output is then measuredwith a DSO. When perceivable, only at high frequencies andoutput level. The curves in TPC 24 show the peak-to-peak out-The majority of the VPHS output data was collected by generatingconfiguration shown in Figure 16. Although this method givescurves showing swept phase, the phase at which the VPHS is the and allother angles are references to there. Typical Performance Curvesshow two figures of merit; instantaneous slope and error. Instanta-neous slope, as shown in TPCs 43, 44, 45, and 47, was angular change for adjacent TEKTRONIX VMAGVREFVPHS SIGNAL GENERATORSMTO3 VX1410A SIGNAL GENERATORSMTO3 SAME SETUP ASV Figure 16.Primary Characterization Setup VMAGVREFVPHS SIGNAL ATTEN VX1410A TDS 744AOSCILLOSCOPE Figure 17.VMAG Dynamic Performance Measurement Setup REV. A AD8302 4.40 71 PIN 15.105.00 PLANE 0.05 1.00 0 0.60 COMPLIANT TO JEDEC STANDARDS MO-153AB-1 (RU-14)Dimensions shown in millimeters REV. AÐ0ÐPRINTED IN U.S.A.Revision History TPCs 3 through 6 replaced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6