SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION - PDF document

- 1 -K4A4G165WERev. 1.4, Jun. 2016SAMS
- 1 -K4A4G165WERev. 1.4, Jun. 2016SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.Products and specifications discussed herein are for reference purposes only. All information discussed may apply.For updates or additional information about Samsung products, contact your nearest Samsung office. All rights reserved.4Gb E-die DDR4 SDRAM96FBGA with Lead-Free & Halogen-Free(RoHS compliant)datasheet- 2 -DDR4 SDRAMRev. 1.4evision HistoryHistoryDraft DateRemark1.0- First SPEC release19th Oct. 2015-J.Y.Lee1.1- Addition of values on page 10 [Table 5]27th Oct. 2015-J.Y.Lee1.2- Addition of Industrial temp11th Apr. 2016-J.Y.Lee1.3- Correction of typo27th May. 2016-J.Y.Lee1.4- Addition of DDR4-266628th Jun. 2016-J.Y.Lee- 3 -DDR4 SDRAMRev. 1.41. Ordering Information.....................................................................................................................................................42. Key Features...................................................

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..............................................................................................................43. Package pinout/Mechanical Dimension & Addressing..................................................................................................53.1 x16 Package Pinout (Top view) : 96ball FBGA Package........................................................................................53.2 FBGA Package Dimension (x16).............................................................................................................................64. Input/Output Functional Description..............................................................................................................................75. DDR4 SDRAM Addressing...........................................................................................................................................96. Absolute Maximum Ratings..................................................................................................................................

........106.1 Absolute Maximum DC Rating
........106.1 Absolute Maximum DC Ratings...............................................................................................................................106.2 DRAM Component Operating Temperature Range................................................................................................107. AC & DC Operating Conditions.....................................................................................................................................108. AC & DC Input Measurement Levels...........................................................................................................................118.1 AC & DC Logic input levels for single-ended signals..............................................................................................118.2 VREF Tolerances....................................................................................................................................................118.3 AC & DC Logic Input Levels for Differential Signals................................

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...............................................................128.3.1. Differential signals definition............................................................................................................................128.3.2. Differential swing requirement for clock (CK_t - CK_c)....................................................................................128.3.3. Single-ended requirements for differential signals...........................................................................................138.3.4. Address, Command and Control Overshoot and Undershoot specifications...................................................18.3.5. Clock Overshoot and Undershoot Specifications.............................................................................................158.3.6. Data, Strobe and Mask Overshoot and Undershoot Specifications.................................................................168.4 Slew Rate Definitions.........................................................................................

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.....................................................178.4.1. Slew Rate Definitions for Differential Input Signals (CK).................................................................................17.........188.5 Differential Input Cross Point Voltage......................................................................................................................198.6 CMOS rail to rail Input Levels..................................................................................................................................208.6.1. CMOS rail to rail Input Levels for RESET_n....................................................................................................208.7 AC and DC Logic Input Levels for DQS Signals......................................................................................................218.7.1. Differential signal definition..............................................................................................................................218.7.2. Differential swing requirements f

or DQS (DQS_t - DQS_c)..................
or DQS (DQS_t - DQS_c).............................................................................218.7.3. Peak voltage calculation method.....................................................................................................................218.7.4. Differential Input Cross Point Voltage..............................................................................................................228.7.5. Differential Input Slew Rate Definition..............................................................................................................239. AC and DC output Measurement levels........................................................................................................................249.1 Output Driver DC Electrical Characteristics.............................................................................................................249.1.1. Alert_n output Drive Characteristic..................................................................................................................26

9.1.2. Output Driver Characteristic of C
9.1.2. Output Driver Characteristic of Connectivity Test ( CT ) Mode........................................................................269.2 Single-ended AC & DC Output Levels.....................................................................................................................279.3 Differential AC & DC Output Levels.........................................................................................................................279.4 Single-ended Output Slew Rate..............................................................................................................................289.5 Differential Output Slew Rate..................................................................................................................................299.6 Single-ended AC & DC Output Levels of Connectivity Test Mode..........................................................................309.7 Test Load for Connectivity Test Mode Timing............................................................................

.............................3010. Speed
.............................3010. Speed Bin...................................................................................................................................................................3110.1 Speed Bin Table Note...........................................................................................................................................3611. IDD and IDDQ Specification Parameters and Test conditions....................................................................................3711.1 IDD, IPP and IDDQ Measurement Conditions.......................................................................................................3711.2 4Gb DDR4 SDRAM E-die IDD Specification Table...............................................................................................5212. Input/Output Capacitance...........................................................................................................................................5413. Electrical Characteristics & AC Timing....................

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...................................................................................................5613.1 Reference Load for AC Timing and Output Slew Rate..........................................................................................5613.2 tREFI.....................................................................................................................................................................5613.3 Timing Parameters by Speed Grade.....................................................................................................................57- 4 -DDR4 SDRAMRev. 1.413.4 The DQ input receiver compliance mask for voltage and timing...........................................................................6313.5 DDR4 Function Matrix...........................................................................................................................................67- 4 -DDR4 SDRAMRev. 1.41. Ordering Information[ Table 1 ] Samsung 4Gb DDR4 E-die ordering information table 1. Speed bin is in order

of CL-tRCD-tRP. 3. 13th digit stands fo
of CL-tRCD-tRP. 3. 13th digit stands for below.2. Key Features[ Table 2 ] 4Gb DDR4 E-die Speed bins22256Mx16K4A4G165WE-BCPBK4A4G165WE-BCRCK4A4G165WE-BCTD96FBGA256Mx16K4A4G165WE-BIPBK4A4G165WE-BIRCK4A4G165WE-BITD96FBGA11-11-110.75 nsCAS Latency19nCK14.25ns14.25ns32ns46.25ns•JEDEC standard 1.2V (1.14V~1.26V) •8 Banks (2 Bank Groups)•Programmable CAS Latency(posted CAS): 10,11,12,13,14,15,16,17,18,19,20•Programmable CAS Write Latency (CWL) = 9,11 (DDR4-1600) , 10,12 (DDR4-1866) ,11,14 (DDR4-2133) ,12,16 (DDR4-2400) and •8-bit pre-fetch•Burst Length: 8 , 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]•Bi-directional Differential Data-Strobe•Internal(self) calibration : Internal self calibration through ZQ pin •On Die Termination using ODT pin•Average Refresh Period 7.8us at lower than T•Support Industrial Temp ( -40 TCASE - tREFI 3.9us at 85 °C TCASE •Asynchronous Reset•Package : 96 balls FBGA - x16•All of Lead-Free products are compliant for RoHS•All of product

s are Halogen-free•CRC(Cyclic Redundancy
s are Halogen-free•CRC(Cyclic Redundancy Check) for Read/Write data security•Command address parity check •DBI(Data Bus Inversion)•Gear down mode• POD (Pseudo Open Drain) interface for data input/output•Internal VREF for data inputs•External VPP for DRAM Activating Power•PPR is supported The chip is designed to comply with the following key DDR4 SDRAM fea- All of the control and address inputs are synchronized with a pair of exter-CK falling). All I/Os are synchronized with a DQS) in a source synchronous fash-ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. The DDR4 device operates : 1. This data sheet is an abstract of full DDR4 specification and does not cover the common features which are described in “DDR4 SDRAM Device Operation & Timing - 5 -DDR4 SDRAMRev. 1.43. Package pinout/Mechanical Dimension & Addressing3.1 x16 Package Pinout (Top view) : 96ball FBGA PackageDBIU_nDBIL_nA14Populated ballBall not populatedTop view123489PRT- 6 -DDR4 SDRAMRev. 1

.43.2 FBGA Package Dimension (x16)BCDE
.43.2 FBGA Package Dimension (x16)BCDEFGHMN0.80 x15 = 12.003.200.80(Datum B)(Datum A)0.10MAX1.10 0.10#A1 1.607.50 0.1013.30 0.100.37 0.05#A1 INDEX MARKBBOTTOM VIEWTOP VIEW13.30 0.10KL0.800.40(Post reflow 0.50 ± 0.05)Units : Millimetersx 8 = 6.40A0.807.50 0.10RTP0.296 - 0.48 Solder ball- 7 -DDR4 SDRAMRev. 1.44. Input/Output Functional Description[ Table 3 ] Input/Output function descriptionTypeCK_t, CK_cInputClock: CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on CKE, (CKE1)Inputbuffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for Self-Refresh exit. After VREFCA and Internal DQ Vref have become stable during the power on and initialization sequence, throughout read and write accesses. Input buffers, excluding CK_t,CK_cduring power-down. Input buffers, excluding CKE, are disabled during Self-Refresh.Chip Select: All com

mands are masked when CS_n is registered
mands are masked when CS_n is registered HIGH. CS_n provides for external Rank Chip ID : Chip ID is only used for 3DS for 2,4,8high stack via TSV to select each slice of stacked ODT, (ODT1)On Die Termination: ODT (registered HIGH) enables RTT_NOM termination resistance internal to the TDQS_t, NU/TDQS_c (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 DMU_n, and DML_n signal. The ODT pin will be ignored if MR1 is programmed to disable RTT_NOM.Activation Command Input : ACT_n defines the Activation command being entered along with CS_n. The input into RAS_n/A16, CAS_n/A15 and WE_n/A14 will be considered as Row Address A16, A15 and A14entered. Those pins have multi function. For example, for activation with ACT_n Low, those are Addressing like A16,A15 and A14 but for non-activation command with ACT_n High, those are Command pins for Read, Write and other command defined in command truth tablemasked when DM_n is sampled LOW coincident with that input data during a Write access. DM_n is sampled on both edges of DQS. DM

is muxed with DBI function by Mode Regi
is muxed with DBI function by Mode Register A10,A11,A12 setting in MR5. For x8 device, the function of DM or TDQS is enabled by Mode Register A11 setting in MR1. DBI_n is an input/output identifing whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/output after inversion inside the DDR4 SDRAM and not inverted if DBI_n is HIGH. TDQS is only Bank Group Inputs : BG0 - BG1 define to which bank group an Active, Read, Write or Precharge command Bank Address Inputs: BA0 - BA1 define to which bank an Active, Read, Write or Precharge command is A0 - A17Address Inputs: Provide the row address for ACTIVATE Commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP, A12/A10 / APAuto-precharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH: Autoprecharge; LOW: no Autoprecharge).A10 is sampled during a Precharge command to

determine whether the Precharge Burst Ch
determine whether the Precharge Burst Chop: A12 / BC_n is sampled during Read and Write commands to determine if burst chop (on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth table for details.Active Low Asynchronous Reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is the end of Data Burst. Any DQ from DQ0~DQ3 may indicate the internal Vref level during test via Mode Register Setting MR4 A4=High. During this mode, RTT value should be set to Hi-Z. Refer to vendor DQU0-DQU7. The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.- 8 -DDR4 SDRAMRev. 1.4Termination Data Strobe: TDQS_t/TDQS_c is applicable for x8 DRAMs only. When enabled via Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function on TDQS_t/TDQS_c that

is applied to DQS_t/DQS_c. When disable
is applied to DQS_t/DQS_c. When disabled via mode register A11 = 0 in MR1, DM/DBI/TDQS will provide the data mask function or Data Bus Inversion depending on MR5; A11,12,10and TDQS_c is not used. x4/x16 DRAMs must disable the TDQS function via mode register A11 = 0 in MR1.PARCommand and Address Parity Input : DDR4 Supports Even Parity check in DRAM with MR setting. Once it’s enabled via Register in MR5, then DRAM calculates Parity with ACT_n,RAS_n/A16,CAS_n/A15,WE_n/ALERT_nAlert : It has multi functions such as CRC error flag , Command and Address Parity error flag as Output signal. If there is error in CRC, then Alert_n goes LOW for the period time interval and goes back HIGH. If there is error in Command Address Parity Check, then Alert_n goes LOW for relatively long period until on going DRAM internal recovery transaction to complete. During Connectivity Test mode, this pin works as Using this signal or not is dependent on system. In case of not connected as Signal, ALERT_n Pin must be Connectivity Test Mode Enable : Required on

X16 devices and optional input on x4/x8
X16 devices and optional input on x4/x8 with densities equal to or greater than 8Gb.HIGH in this pin will enable Connectivity Test Mode operation along with other pins. It is a CMOS rail to rail signal with AC high and low at 80% and 20% of VDD. Using this signal or not is dependent on System. This pin may be DRAM internally pulled low through a weak pull-down resistor to SupplyDQ Power Supply: 1.2 V +/- 0.06 VDRAM Activating Power Supply: 2.5V ( 2.375V min , 2.75V max)NOTE Input only pins (BG0-BG1,BA0-BA1, A0-A17, ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, CS_n, CKE, ODT, and RESET_n) do not supType- 9 -DDR4 SDRAMRev. 1.45. DDR4 SDRAM AddressingAddressing Table4 Gb Addressing Table8 Gb Addressing Table16 Gb Addressing TableNOTE 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG8 where, COLBITS = the number of co

lumn address bits, ORG = the number
lumn address bits, ORG = the number of I/O (DQ) bits# of Bank Groups442BG AddressBG0~BG1BG0~BG1BG0Bank Address in a BGBA0~BA1BA0~BA1BA0~BA1Row AddressA0~A14A0~A13A0~A13Column AddressA0~A9A0~A9A0~A9Page size512B1KB2KB# of Bank Groups442BG AddressBG0~BG1BG0~BG1BG0Bank Address in a BGBA0~BA1BA0~BA1BA0~BA1Row AddressA0~A15A0~A14A0~A14Column AddressA0~A9A0~A9A0~A9Page size512B1KB2KB# of Bank Groups442BG AddressBG0~BG1BG0~BG1BG0Bank Address in a BGBA0~BA1BA0~BA1BA0~BA1Row AddressA0~A16A0~A15A0~A15Column AddressA0~A9A0~A9A0~A9Page size512B1KB2KB# of Bank Groups442BG AddressBG0~BG1BG0~BG1BG0Bank Address in a BGBA0~BA1BA0~BA1BA0~BA1Row AddressA0~A17A0~A16A0~A16Column AddressA0~A9A0~A9A0~A9Page size512B1KB2KB- 10 -DDR4 SDRAMRev. 1.46. Absolute Maximum Ratings6.1 Absolute Maximum DC Ratings[ Table 4 ] Absolute Maximum DC Ratings1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stre Exposure to absolute maximum rating conditions for extended periods may affect

reliability2. Storage Temperature is the
reliability2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, pleaDDQ are less than 500 mV; VREFCA 6.2 DRAM Component Operating Temperature Range[ Table 5 ] Temperature RangeNOTE :1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, t-tained between 0-85C under all operating conditions3. The Industrial Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operatio-tained between -40-95C under all operating conditions4. Some applications require operation of the Extended Temperature Range between 85a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the Manual Self-Refresh mode

with Extended Temperature Range capabil
with Extended Temperature Range capability (MR2 A6 = 0 and MR2 A7 = 17. AC & DC Operating Conditions[ Table 6 ] Recommended DC Operating ConditionsVoltage on VDD pin relative to Vss-0.3 ~ 1.5V 1,3Voltage on VDDQ pin relative to Vss-0.3 ~ 1.5V 1,3Voltage on VPP pin relative to Vss-0.3 ~ 3.0V4Voltage on any pin except VREFCA relative to Vss-0.3 ~ 1.5V 1,3,5Storage Temperature -55 to +100°C 1,2Operating Temperature Range Normal 0 to 95C1, 2, 4Industrial -40 to 95 C1, 3, 4Typ.VDDSupply Voltage1.141.21.26V1,2,3VDDQSupply Voltage for Output1.141.21.26V1,2,3VPPPeak-to-Peak Voltage2.3752.52.75V3- 11 -DDR4 SDRAMRev. 1.48. AC & DC Input Measurement Levels8.1 AC & DC Logic input levels for single-ended signals[ Table 7 ] Single-ended AC & DC input levels for Command and Address8.2 VREF Tolerances is illustrated in Figure 1. It shows a valid reference voltage V(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on 11. Furthermore V The voltage levels for setup and ho

ld time measurements V 1 . This clarifie
ld time measurements V 1 . This clarifies, that dc-variations of V affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated wit ac-noise. Timing and voltage effects due to ac-noise on VE(DC75)DC input logic high V+ 0.075 VTBDTBDV(DC75) DC input logic low V-0.075 TBDTBDV(AC100) AC input logic high V+ 0.1 Note 2 TBDTBDV1(AC100) AC input logic low Note 2 V- 0.1 TBDTBDV1(DC) Reference Voltage for ADD, CMD inputs 0.49*VTBDTBDV2,3voltageVDDVSStime- 12 -DDR4 SDRAMRev. 1.48.3 AC & DC Logic Input Levels for Differential Signals8.3.1 Differential signals definitionFigure 2. Definition of differential ac-swing and "time above ac level" tDVAC8.3.2 Differential swing requirement for clock (CK_t - CK_c)[ Table 8 ] Differential AC & DC Input Levels1. Used to define a differential signal slew-rate.(AC) of ADD/CMD and V3. These values are not defined; however, th

e differential signals CK_t - CK_c, need
e differential signals CK_t - CK_c, need to be within the respective limits (VIHdiffdifferential input high+0.150NOTE 3 TBDNOTE 3 V1ILdiffdifferential input low NOTE 3 -0.150NOTE 3 TBDV1IHdiffdifferential input high acNOTE 3 V2ILdiffdifferential input low acNOTE 3 2 x (V 2 x (VtDVAC.DIFF.MINDifferential Input Voltage (i.e. DQS-DQS, CK-CK)tDVAC.DIFF.AC.MIN.DIFF.MAX.DIFF.AC.MAX- 13 -DDR4 SDRAMRev. 1.4[ Table 9 ] Allowed time before ringback (tDVAC) for CK_t - CK_c8.3.3 Single-ended requirements for differential signalsEach individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended sferential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended sIH.CA(AC) / VIL.CA(AC)} for ADD/CMD signals] Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g. if Different value than VNote that while ADD/CMD signal requirements are with respect to V, the single-ended components of differential signals have a requiremen

t with /2; this is nominally the same. T
t with /2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VtDVAC [ps] @ |V� 4.0120-4.0115-3.0110-2.0105-1.8100-1.695-1.490-1.285-1.080-80-VDD or VDDQVSEH minVDD/2 or VDDQ/2VSEL maxVSEHVSS or VSSQVSEL CK time- 14 -DDR4 SDRAMRev. 1.4[ Table 10 ] Single-ended levels for CK_t, CK_c(AC) of ADD/CMD;(AC) for ADD/CMD is based on V3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (V8.3.4 Address, Command and Control Overshoot and Undershoot specifications[ Table 11 ] AC overshoot/undershoot specification for Address, Command and Control pinsFigure 4. Address, Command and Control Overshoot and Undershoot Definition(VDD/2)+0.100NOTE3TBDNOTE3V1, 2NOTE3(VDD/2)-0.100NOTE3TBDV1, 20.06 0.06 0.06 0.06 TBDV0.24 0.24 0.24 0.24 TBDVMaximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBDV-ns0.00830.007

10.00620.0055TBDV-nsMaximum overshoot ar
10.00620.0055TBDV-nsMaximum overshoot area per 1tCK Between Absolute Max and VDD Max 0.25500.21850.19140.1699TBDV-nsMaximum undershoot area per 1tCK Below VSS 0.2644 0.22650.19840.1762TBDV-nsOvershoot Area BetweenVDDVoltsVDD Absolute Max and VDD Max1 tCKVDD Absolute MaxOvershoot Area above VDD Absolute Max- 15 -DDR4 SDRAMRev. 1.48.3.5 Clock Overshoot and Undershoot Specifications[ Table 12 ] AC overshoot/undershoot specification for ClockFigure 5. Clock Overshoot and Undershoot Definition0.06 0.06 0.06 0.06 TBDV0.24 0.24 0.24 0.24 TBDVMaximum peak amplitude allowed for undershoot area 0.3 0.3 0.3 0.3 TBDVMaximum overshoot area per 1UI Above Absolute Max 0.00380.00320.00280.0025TBDV-nsMaximum overshoot area per 1UI Between Absolute Max and VDD Max 0.11250.09640.08440.0750TBDV-nsMaximum undershoot area per 1UI Below VSS 0.11440.09800.08580.0762TBDV-nsVDDVoltsVDD Absolute Max and VDD Max1UIVDD Absolute MaxOvershoot Area above VDD Absolute Max- 16 -DDR4 SDRAMRev. 1.48.3.6 Data, Strobe and Mask Overshoot and Undershoo

t Specifications[ Table 13 ] AC oversho
t Specifications[ Table 13 ] AC overshoot/undershoot specification for Data, Strobe and MaskFigure 6. Data, Strobe and Mask Overshoot and Undershoot DefinitionMaximum peak amplitude above Max absolute level of Vin, Vout 0.16 0.16 0.16 0.16 TBDVOvershoot area Between Max Absolute level of Vin, Vout and VDDQ Max0.240.240.240.24TBDVUndershoot area Between Min absolute level of Vin, Vout and VSSQ0.300.300.300.30TBDVMaximum peak amplitude below Min absolute level of Vin, Vout 0.100.100.100.10TBDVMaximum overshoot area per 1UI Above Max absolute level of Vin, Vout 0.01500.01290.01130.0100TBDV-ns0.10500.09000.07880.0700TBDV-ns0.10500.09000.07880.0700TBDV-nsMaximum undershoot area per 1UI Below Min absolute level of Vin,Vout 0.01500.01290.01130.0100TBDV-nsOvershoot Area BetweenVDDQVoltsMax absolute level of Vin,Vout and VDDQ Max1UIMax absolute level of Vin, VoutOvershoot area above Max absolute level of Vin,VoutMin absolute level of Vin, VoutMin absolute level of Vin,Vout and VSSQUndershoot area below Min absolute level of Vin,Vou

t- 17 -DDR4 SDRAMRev. 1.48.4 Slew Rat
t- 17 -DDR4 SDRAMRev. 1.48.4 Slew Rate Definitions 8.4.1 Slew Rate Definitions for Differential Input Signals (CK)Input slew rate for differential signals (CK_t, CK_c) are defined and measured as shown in Table 14 and Figure 7.[ Table 14 ] Differential input slew rate definitionThe differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds.Figure 7. Differential Input Slew Rate definition for CK, CK ILdiffmaxIHdiffminIHdiffmin - ILdiffmax Differential input slew rate for falling edge(CK_t - CK_c)IHdiffminILdiffmaxIHdiffmin - ILdiffmax Delta TRdiffDelta TFdiffIHdiffminILdiffmaxDifferential Input Voltage(i,e, CK_t - CK_c)- 18 -DDR4 SDRAMRev. 1.48.4.2 Slew Rate Definition for Single-ended Input Signals ( CMD/ADD )1. Single-ended input slew rate for rising edge = { VIHCA(AC)Min - VILCA(DC)Max } / Delta TR single2. Single-ended input slew rate for falling edge = { VIHCA(DC)Min - VILCA(AC)Max } / Delta TF singleFigure 8. Single-ended Input Slew Rate definition for CMD and ADDDelta TRsingleDe

lta TFsingleVIHCA(AC) MinVIHCA(DC) MinV
lta TFsingleVIHCA(AC) MinVIHCA(DC) MinVREFCA(DC)VILCA(DC) MaxVILCA(AC) Max- 19 -DDR4 SDRAMRev. 1.48.5 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as output skew parameters with respect to clock, each cross point voltage of differential input signals (CK_t, CK_c) must meet the requirements in Table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS. Figure 9. Vix Definition (CK)[ Table 15 ] Cross point voltage for differential input signals (CK)-Area of VSEH, VSEL-Area of VSEH, VSELTBDTBDTBDTBDTBDTBDTBDTBDVixVDD/2VSSVDDCK_cVixVSEH- 20 -DDR4 SDRAMRev. 1.48.6 CMOS rail to rail Input Levels8.6.1 CMOS rail to rail Input Levels for RESET_n [ Table 16 ] CMOS rail to rail Input Levels for RESET_nFigure 10. RESET_n Input Slew Rate Definition AC Input High Voltage VIH(AC)_RESET 0.8*VDDVDDV6DC Input High Voltage VIH(DC)_RESET 0.7*VDDVDDV2DC Input Low Voltage VIL(DC)_RESET VSS0.3

*VDDV1AC Input Low Voltage VIL(AC)_RESET
*VDDV1AC Input Low Voltage VIL(AC)_RESET VSS0.2*VDDV7Rising time TR_RESET -1.0us4RESET pulse width tPW_RESET 1.0-us3,50.8*VDDTR_RESETtPW_RESET0.7*VDD0.3*VDD0.2*VDD- 21 -DDR4 SDRAMRev. 1.48.7 AC and DC Logic Input Levels for DQS Signals8.7.1 Differential signal definitionFigure 11. Definition of differential DQS Signal AC-swing Level8.7.2 Differential swing requirements for DQS (DQS_t - DQS_c)[ Table 17 ] Differential AC and DC Input Levels for DQS8.7.3 Peak voltage calculation methodThe peak voltage of Differential DQS signals are calculated in a following equation.VIH.DIFF.Peak Voltage = Max(f(t))VIL.DIFF.Peak Voltage = Min(f(t))VIHDiffPeakVIH.DIFF.Peak Voltage186Note2160Note2TBDTBDmV1VILDiffPeakVIL.DIFF.Peak VoltageNote2-186Note2-160TBDTBDmV1- 22 -DDR4 SDRAMRev. 1.4Figure 12. Definition of differential DQS Peak Voltage8.7.4 Differential Input Cross Point VoltageTo guarantee tight setup and hold times as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS

_t, DQS_c) must meet the requirements in
_t, DQS_c) must meet the requirements in Table 18. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the mid level that is VrefDQ.Vix Definition (DQS)Figure 13. Vix Definition (DQS)- 23 -DDR4 SDRAMRev. 1.4[ Table 18 ] Cross point voltage for differential input signals (DQS)8.7.5 Differential Input Slew Rate DefinitionInput slew rate for differential signals (DQS_t, DQS_c) are defined and measured as shown in are Figure11 and Figure 12.Figure 14. Differential Input Slew Rate Definition for DQS_t, DQS_c[ Table 19 ] Differential Input Slew Rate Definition for DQS_t, DQS_c[ Table 20 ] Differential Input Level for DQS_t, DQS_c[ Table 21 ] Differential Input Slew Rate for DQS_t, DQS_c-25TBDTBD%1, 2, 3Differential input slew rate for rising edge(DQS_t - DQS_c)VILDiff_DQSVIHDiff_DQS|VILDiff_DQS - VIHDiff_DQS|/DeltaTRdiffDifferential input slew rate for falling edge(DQS_t - DQS_c)VIHDiff_DQSVILDiff_DQS|VILDiff_DQS - VIHDiff_DQS|/DeltaTFdiffVIHDiff_DQSDifferntial

Input High136-130-TBDTBDmVVILDiff_DQSDif
Input High136-130-TBDTBDmVVILDiff_DQSDifferntial Input Low--136--130TBDTBDmVSRIdiffDifferential Intput Slew Rate318TBDTBDV/ns- 24 -DDR4 SDRAMRev. 1.49. AC and DC output Measurement levels9.1 Output Driver DC Electrical Characteristics The DDR4 driver supports two different Ron values. These Ron values are referred as strong(low Ron) and weak mode(high Ron). A functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows: The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: Figure 15. Output driverVDDQ -VoutI outis offVoutI outis offRCV, ...DQPuVSSQVDDQIoutVoutChip In Drive ModeRONPdIPuIPd- 25 -DDR4 SDRAMRev. 1.4[ Table 22 ] Output Driver DC Electrical Characteristics, assuming RZQ=240ohm; entire operating temperature range; NOMVoutVOLdc= 0.5*VDDQ 0.811.1RZQ/71,2VOMdc= 0.8* VDDQ 0.911.1RZQ/71,2VOHdc= 1.1* VDDQ 0.911.25RZQ/71,2VOLdc= 0.5* VDDQ 0.911.25RZQ/71,2VOMdc= 0.8* VDDQ 0.911.1RZQ/71,2VOHdc= 1.1* VDDQ 0.811

.1RZQ/71,2VOLdc= 0.5*VDDQ 0.811.1RZQ/51
.1RZQ/71,2VOLdc= 0.5*VDDQ 0.811.1RZQ/51,2VOMdc= 0.8* VDDQ 0.911.1RZQ/51,2VOHdc= 1.1* VDDQ 0.911.25RZQ/51,2VOLdc= 0.5* VDDQ 0.911.25RZQ/51,2VOMdc= 0.8* VDDQ 0.911.1RZQ/51,2VOHdc= 1.1* VDDQ 0.811.1RZQ/51,2VOMdc= 0.8* VDDQ -10-10% 1,2,3,4VOMdc= 0.8* VDDQ --10% 1,2,4VOMdc= 0.8* VDDQ --10% 1,2,4MMPuPd = RONPu -RONPdRONNOM*100MMPudd = RONPuMax -RONPuMinRONNOM*100MMPddd = RONPdMax -RONPdMinRONNOM*100- 26 -DDR4 SDRAMRev. 1.49.1.1 Alert_n output Drive CharacteristicA functional representation of the output buffer is shown in the figure below. Output driver impedance RON is defined as follows: NOTE : 1. VDDQ voltage is at VDDQ DC. VDDQ DC definition is TBD.9.1.2 Output Driver Characteristic of Connectivity Test ( CT ) Mode Following Output driver impedance RON will be applied Test Output Pin during Connectivity Test ( CT ) Mode. The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows: Figure 16. Output DriverVoutVOLdc= 0.1* VDDQ 0.31.2340.41.2340.41.434Vout is offDRAMAlertVSSQIoutVout

RONPdIPdAlert DriverRONPu_CT =VDDQ-VOUTl
RONPdIPdAlert DriverRONPu_CT =VDDQ-VOUTl Iout lRONPd_CT =VOUTl Iout lVDDQDQVSSQRONPu_CTPd_CTRONPd_CTRCV,...Chip In Driver Mode- 27 -DDR4 SDRAMRev. 1.49.2 Single-ended AC & DC Output Levels[ Table 23 ] Single-ended AC & DC output levels1. The swing of ± 0.15 × V is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test 9.3 Differential AC & DC Output Levels[ Table 24 ] Differential AC & DC output levels1. The swing of ± 0.3 × V is based on approximately 50% of the static differential output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load at each of the differential outputs.NOM_CTVout1.9342.0342.2342.5342.5342.2342.0341.934(DC)DC output high measurement level (for IV curve linearity)1.1 x V(DC)DC output mid measurement level (for IV curve linearity)0.8 x V(DC)DC output low measurement level (for IV curve linearity)0.5 x V(AC)AC output high measurement level (for output SR)(0.7 + 0.15) x V(AC)AC output low meas

urement level (for output SR)(0.7 - 0.15
urement level (for output SR)(0.7 - 0.15) x VOHdiff(AC)AC differential output high measurement level (for output SR)+0.3 x VOLdiff(AC)AC differential output low measurement level (for output SR)-0.3 x V- 28 -DDR4 SDRAMRev. 1.49.4 Single-ended Output Slew Ratesingle ended signals as shown in Table 25 and Figure 17.[ Table 25 ] Single-ended output slew rate definition[ Table 26 ] Single-ended output slew rateDescription: SR: Slew RateQ: Query Output (like in DQ, which stands for Data-in, Query-Output)se: Single-ended SignalsFor Ron = RZQ/7 settingNOTE :1. In two cases, a maximum slew rate of 12 V/ns applies for a single DQ signal within a byte lane.-Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). DQ signal switching into the opposite direction, the (AC)V(AC) [V(AC)] / Delta TRse(AC)V(AC)[V(AC)] / Delta TFseSingle ended outp

ut slew rate SRQse49494949TBDTBDVOH(AC)
ut slew rate SRQse49494949TBDTBDVOH(AC) VOL(AC) delta TRsedelta TFseVTT - 29 -DDR4 SDRAMRev. 1.49.5 Differential Output Slew RateVOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 27 and Figure 18.[ Table 27 ] Differential output slew rate definition[ Table 28 ] Differential output slew rateDescription:SR: Slew RateQ: Query Output (like in DQ, which stands for Data-in, Query-Output)diff: Differential SignalsFor Ron = RZQ/7 settingDifferential output slew rate for rising edgeOLdiff(AC)VOHdiff(AC)[VOHdiffOLdiff(AC)] / Delta TRdiffDifferential output slew rate for falling edgeOHdiff(AC)VOLdiff(AC)[VOHdiffOLdiff(AC)] /Delta TFdiffDifferential output slew rate SRQdiff818818818818TBDTBDV/nsOHdiffOLdiffTRdiffTFdiffVTT - 30 -DDR4 SDRAMRev. 1.49.6 Single-ended AC & DC Output Levels of Connectivity Test Mode[ Table 29 ] Single-ended AC & DC output levels of Connectivity Test ModeFigure 19. Output Slew Rate Definition of Connectivity Test Mode[ Table 30 ] Single-ended output slew rate of Connectivity T

est Mode9.7 Test Load for Connectivity
est Mode9.7 Test Load for Connectivity Test Mode Timing 18Figure 20. Connectivity Test Mode Timing Reference Load 1.1 x VDDQ VDC output mid measurement level (for IV curve linearity) 0.8 x VDDQ VDC output low measurement level (for IV curve linearity) 0.5 x VDDQ VDC output below measurement level (for IV curve linearity) 0.2 x VDDQ VAC output high measurement level (for output SR) VTT + (0.1 x VDDQ) V1VTT - (0.1 x VDDQ) V1Output signal Falling time TF_output_CT -10ns/VTR_output_CT -10ns/VVOH(AC) TR_output_CTVTT VOL(AC) TR_output_CT0.5 * VDDQVDDQCT_INPUTSDQ, DMDQSU , DQSUDQS , DQSTiming Reference PointsDQSL0.5*VDDQ- 31 -DDR4 SDRAMRev. 1.410. Speed Bin [ Table 31 ] DDR4-1600 Speed Bins and Operations11-11-11Internal read command to first data tAA 18.00 ns 11Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns11ACT to internal read or write delay time tRCD - ns 11PRE command period tRP - ns 11ACT to PRE command period tRAS 35 9 x tREFI ns 11ACT to ACT or REF command pe

riod tRC - ns 11NormalRead DBICL = 9CL =
riod tRC - ns 11NormalRead DBICL = 9CL = 11tCK(AVG) 1.6ns 1,2,3,4,10,13CL = 10CL = 12tCK(AVG) Reservedns 1,2,3,4,10CWL = 9,11 CL = 10CL = 12tCK(AVG) Reservedns 1,2,3,4CL = 11CL = 13tCK(AVG) 1.25ns 1,2,3,4CL = 12CL = 14tCK(AVG) 1.25ns 1,2,3Supported CL Settings 9,11,12 nCK 12,13Supported CL Settings with read DBI 11,13,14 nCK 13Supported CWL Settings 9,11nCK - 32 -DDR4 SDRAMRev. 1.4[ Table 32 ] DDR4-1866 Speed Bins and OperationsInternal read command to first data tAA 18.00 ns 11Internal read command to first data with read DBI enabled tAA_DBI tAA(min) + 2nCK tAA(max) +2nCK ns11ACT to internal read or write delay time tRCD - ns 11PRE command period tRP - ns 11ACT to PRE command period tRAS 349 x tREFI ns 11ACT to ACT or REF command period tRC - ns 11Normal Read DBI CL = 9CL = 11tCK(AVG) 1.6ns 1,2,3,4,10,13CL = 10CL = 12tCK(AVG) Reservedns 1,2,3,4,10CWL = 9,11CL = 10CL = 12tCK(AVG) Reservedns 4CL = 11CL = 13tCK(AVG) 1.25CL = 12CL = 14tCK(AVG) 1.25ns 1,2,3,6CL = 12CL = 14tCK(AVG) Reservedns 1,2,3,4CL = 13CL = 15tCK(AVG) 1.071ns 1,2,3

,4CL = 14CL = 16tCK(AVG) 1.071ns 1,2,3Su
,4CL = 14CL = 16tCK(AVG) 1.071ns 1,2,3Supported CL Settings 9,11,12,13,14nCK 12,13Supported CL Settings with read DBI 11,13,14,15,16nCK 13Supported CWL Settings 9,10,11,12nCK - 33 -DDR4 SDRAMRev. 1.4[ Table 33 ] DDR4-2133 Speed Bins and OperationsInternal read command to first data tAA 18.00 ns 11tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11ACT to internal read or write delay time tRCD - ns 11PRE command period tRP - ns 11ACT to PRE command period tRAS 339 x tREFI ns 11ACT to ACT or REF command period tRC - ns 11Normal Read DBI CL = 9CL = 11tCK(AVG) 1.6ns CL = 10CL = 12tCK(AVG) Reservedns 1,2,3,10CWL = 9,11CL = 11CL = 13tCK(AVG) 1.25CL = 12CL = 14tCK(AVG) 1.25ns1,2,3,7CL = 13CL = 15tCK(AVG) 1.071CL = 14CL = 16tCK(AVG) 1.071ns 1,2,3,7CWL = 11,14CL = 14CL = 17tCK(AVG) Reservedns 1,2,3,4CL = 15CL = 18tCK(AVG) 0.937ns 1,2,3,4CL = 16CL = 19tCK(AVG) 0.937ns 1,2,3Supported CL Settings 9,11.12,13,14,15,16nCK 12,13Supported CL Settings with read DBI 11,13,14,15,16,18,19 nCK Supported CWL Settings 9,10,11,12,14nCK - 34 -DDR4 SDRAMRev. 1.4

[ Table 34 ] DDR4-2400 Speed Bins and Op
[ Table 34 ] DDR4-2400 Speed Bins and OperationsInternal read command to first data tAA 18.00 ns 11tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11ACT to internal read or write delay time tRCD - ns 11PRE command period tRP - ns 11ACT to PRE command period tRAS 329 x tREFI ns 11ACT to ACT or REF command period tRC - ns 11Normal Read DBI CL = 9CL = 11tCK(AVG) Reservedns 1,2,3,4,10CL = 10CL = 12tCK(AVG) 1.51.6ns 1,2,3,4,10CWL = 9,11CL = 10CL = 12tCK(AVG) Reservedns 4CL = 11CL = 13tCK(AVG) 1.25CL = 12CL = 14tCK(AVG) 1.25ns1,2,3,8CL = 12CL = 14tCK(AVG) Reservedns4CL = 13CL = 15tCK(AVG) 1.071ns 1,2,3,4,8CL = 14CL = 16tCK(AVG) 1.071ns 1,2,3,8CWL = 11,14CL = 14CL = 17tCK(AVG) Reservedns 4CL = 15CL = 18tCK(AVG) 0.938ns 1,2,3,4,8CL = 16CL = 19tCK(AVG) 0.938ns 1,2,3,8CL = 15CL = 18tCK(AVG) Reservedns 1,2,3,4CL = 16CL = 19tCK(AVG) Reservedns 1,2,3,4CL = 17CL = 20tCK(AVG)0.833CL = 18CL = 21tCK(AVG) 0.833ns 1,2,3Supported CL Settings 10,11,12,13,14,15,16,17,18nCK 12Supported CL Settings with read DBI 12,13,14,15,16,18,19,20,21nCK Supported CWL Setti

ngs 9,10,11,12,14,16nCK - 35 -DDR4 SDR
ngs 9,10,11,12,14,16nCK - 35 -DDR4 SDRAMRev. 1.4[ Table 35 ] DDR4-2666 Speed Bins and OperationsInternal read command to first data tAA 5,1118.00 ns 11tAA_DBI tAA(min) + 3nCK tAA(max) + 3nCK ns 11ACT to internal read or write delay time tRCD 5,11- ns 11PRE command period tRP 5,11- ns 11ACT to PRE command period tRAS 329 x tREFI ns 11ACT to ACT or REF command period tRC 5,11- ns 11Normal Read DBI CL = 9CL = 11tCK(AVG) Reservedns 1,2,3,4,11CL = 10CL = 12tCK(AVG) 1.51.6ns 1,2,3,11CWL = 9,11CL = 10CL = 12tCK(AVG) Reservedns 4CL = 11CL = 13tCK(AVG) 1.255,11CL = 12CL = 14tCK(AVG) 1.25ns1,2,3,9CL = 12CL = 14tCK(AVG) Reservedns4CL = 13CL = 15tCK(AVG) 1.0715,11CL = 14CL = 16tCK(AVG) 1.071ns 1,2,3,9CWL = 11,14CL = 14CL = 17tCK(AVG) Reservedns 4CL = 15CL = 18tCK(AVG) 0.9375,11CL = 16CL = 19tCK(AVG) 0.937ns 1,2,3,9CL = 15CL = 18tCK(AVG) Reservedns 4CL = 16CL = 19tCK(AVG) Reservedns CL = 17CL = 20tCK(AVG)0.8335,11CL = 18CL = 21tCK(AVG) 0.833ns 1,2,3CL = 17CL = 20tCK(AVG) Reservedns CL = 18CL = 21tCK(AVG) Reservedns CL = 19CL = 22tCK(AVG) 0.75n

s CL = 20CL = 23tCK(AVG) 0.75ns 1,2,3Sup
s CL = 20CL = 23tCK(AVG) 0.75ns 1,2,3Supported CL Settings 10,11,12,13,14,15,16,17,18,19,20nCK 12Supported CL Settings with read DBI 12,13,14,15,17,18,19,20,21,22,23nCK Supported CWL Settings 9,10,11,12,14,16,18nCK - 36 -DDR4 SDRAMRev. 1.410.1 Speed Bin Table NoteAbsolute Specification - VDDQ = VDD = 1.20V +/- 0.06 V - VPP = 2.5V +0.25/-0.125 V - DDR4-1600, 1866, 21332400and 2666 Speed Bin Tables are valid only when Geardown Mode is disabled.1. The CL setting and CWL setting result in tCK(avg).MIN and tCK(avg).MAX requirements. When making a selection of tCK(avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(avg).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(avg) value (1.5, 1.25, 1.071, 0.938 or 0.833 ns) when calculating CL [nCK] = tAA [ns] / tCK(avg) [ns], rounding up to the next ‘Support

ed CL’, where tAA = 12.5ns and tCK(avg)
ed CL’, where tAA = 12.5ns and tCK(avg) = 1.3 ns should only be used for CL = 10 calculation. 3. tCK(avg).MAX limits: Calculate tCK(avg) = tAA.MAX / CL SELECTED and round the resulting tCK(avg) down to the next valid speed bin (i.e. 1.5ns or 1.25ns or 1.071 ns or 0.938 ns or 0.833 ns). This result is tCK(avg).MAX corresponding to CL SELECTED. 4. ‘Reserved’ settings are not allowed. User must program a different value. efer to supplier's data sheet and/or the DIMM SPD information if and how this setting is supported. 6. Any DDR4-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR4-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR4-2400 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but

verified by Design/Characterization. 9.
verified by Design/Characterization. 9. Any DDR4-2666 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 10 DDR4-1600 AC timing apply if DRAM operates at lower than 1600 MT/s data rate. s. 12. CL number in parentheses, it means that these numbers are optional. 14. Each speed bin lists the timing requirements that need to be supported in order for a given DRAM to be JEDEC compliant. JEDEC compliance does not require support for all speed bins within a given speed. JEDEC compliance requires meeting the parameters for a least one of the listed speed bins.- 37 -DDR4 SDRAMRev. 1.411. IDD and IDDQ Specification Parameters and Test condi-tions11.1 IDD, IPP and IDDQ Measurement ConditionsIn this chapter, IDD, IPP and IDDQ measurement conditions such as test load and patterns are defined. Figure 21 shows the setup and test load for IDD, lIDD currents (such as IDD0, IDD0A, IDD1, IDD1A, IDD2N, IDD2NA, IDD2NL, IDD2NT, I

DD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R
DD2P, IDD2Q, IDD3N, IDD3NA, IDD3P, IDD4R, IDD4IDD4W, IDD4WA, IDD5B, IDD5F2, IDD5F4, IDD6N, IDD6E, IDD6R, IDD6A, IDD7 and IDD8) are measured as time-averaged currents with alballs of the DDR4 SDRAM under test tied together. Any IPP or IDDQ current is not included in IDD currents.lIPP currents have the same definition as IDD except that the current on the VPP supply is measured.lIDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR4 SDRAM under together. Any IDD current is not included in IDDQ currents. Attention: IDDQ values cannot be directly used to calculate IO power of the DDR4 SDRAM. They can be used to support correlationFigure 22. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD, IPP and IDDQ measurements, the following definitions apply:l“0” and “LOW” is defined as VIN l�“1” and “HIGH” is defined as VIN = Vl“MID-LEVEL” is defined as inputs are VREF = VDD / 2.l

Timings used for IDD, IPP and IDDQ Measu
Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns are provided in Table 36.lBasic IDD, IPP and IDDQ Measurement Conditions are described in Table 37.lDetailed IDD, IPP and IDDQ Measurement-Loop Patterns are described in Table 38 through Table 46.lIDD Measurements are done after properly initializing the DDR4 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); RTT_NOM = RZQ/6 (40 Ohm in MR1); RTT_WR = RZQ/2 (120 Ohm in MR2); RTT_PARK = Disable; Qoff = 0B (Output Buffer enabled) in MR1; TDQS_t disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR5; Read/Write DBI disabled in MR5; lAttention: The IDD, IPP and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ mealDefine D = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, LOW, LOW, LOW, LOW} ; apply BG/BA changes when directed.lDefine D# = {CS_n, ACT_n, RAS_n, CAS_n, WE_n } := {HIGH, HIGH, HIGH, HIGH, HIGH} apply invert of BG/

BA changes when directed a- 38 -DDR4 S
BA changes when directed a- 38 -DDR4 SDRAMRev. 1.41. DIMM level Output test load condition may be different from aboveFigure 21. Measurement Setup and Test Load for IDD, IPP and IDDQ MeasurementsFigure 22. Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement.CK_t/CK_cCKECSACT,A,BG,BACODTZQDQS_t/DQS_cDQDMDDR4 SDRAMVSSVSSQVDDVPPVDDQIDDIPPIDDQXApplication specificmemory channelenvironmentChannelIO PoweSimulatinXChannel IO PowerNumberTestLadCorrelation- 39 -DDR4 SDRAMRev. 1.4[ Table 36 ] Timings used for IDD, IPP and IDDQ Measurement-Loop Patterns11-11-11tCK1.251.0710.9380.833TBDnsCL11131517TBDnCKCWL11121416TBDnCKnRCD11131517TBDnCKnRC39455156TBDnCKnRAS28323639TBDnCKnRP11131517TBDnCKx416161616TBDnCKx820222326TBDnCKx1628283236TBDnCKx44444TBDnCKx84444TBDnCKx165567TBDnCKx45566TBDnCKx85566TBDnCKx166678TBDnCKtCCD_S4444TBDnCKtCCD_L5566TBDnCKtWTR_S2333TBDnCKtWTR_L6789TBDnCKnRFC 2Gb128150171193TBDnCKnRFC 4Gb208243278313TBDnCKnRFC 8Gb280327374421TBDnCK- 40 -DDR4 SDRAMRev. 1.4[ T

able 37 ] Basic IDD, IPP and IDDQ Measur
able 37 ] Basic IDD, IPP and IDDQ Measurement Conditions: see Table 36 on page 39; High between ACT and PRE; Command, Address, Bank Group Address, Bank Address Inputs: partially toggling according to Table 38 on page 43; VDDQ; Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 38 on page 43); RTT: see Table 38 on page 43 36 on page 39; 39 on 44; 39 on page 44); 39 on page 44 On; 36 on page 39; 0; partially toggling according to Table 40 on page 45; VDDQ; 40 on 45 On; 36 on page 39; 0; 41 on page 46; 41 on page 46; 41 on page 46 36 on page 39; On; 36 on page 39; 0; stable at 0; VDDQ; all banks closed; On; 36 on page 39; 0; 40 on page 45; Enabled in Mode Registers stable at 0; see Table 40 on page 45- 41 -DDR4 SDRAMRev. 1.4 Low; On; 36 on page 39; 0; : stable at 1; 36 on page 39; partially toggling according to Table 42 on page 47; seamless read data burst 47; 42 on page 47); 42 on page 47 36 on page 39; partially toggling according to Table 43 on page 48; seamless write data

burst 43 on page 48; 43 on page 48);
burst 43 on page 48; 43 on page 48); 43 on page 48 36 on page 39; 45 on page 50; 45 on page 50); 45 on page 50- 42 -DDR4 SDRAMRev. 1.4 0 - 85°C; Off; CK_t and CK_c#: LOW; 36 on page 39; 0 - 95°C; Off; CK_t and CK_c: LOW; 36 on page 39; Extended Temperature Self-Refresh operation; Enabled in Mode Registers MID- 0 - 45°C; Off; CK_t and CK_c#: LOW; 36 on page 39; 0; High; Extended Temperature Self-Refresh operation; Enabled in Mode Registers MID- 36 on page 39; 0; High; 36 on page 39; 46 on 51; read data bursts with different data between one burst and the next one according to Table 46 on page 51; 51; 46 on page 51- 43 -DDR4 SDRAMRev. 1.4[ Table 38 ] IDD0, IDD0A and IPP0 Measurement-Loop PatternNumberCAS_n/ A15WE_n/ A14ODT32A[13,11]000000000000000-1,2D, D100000000000000-3,4D_#, D_#111110030007F0-...repeat pattern 1...4 until nRAS - 1, truncate if necessarynRASPRE010100000000000-...repeat pattern 1...4 until nRC - 1, truncate if necessary11*nRC1*nRC2 = 1, BA[1:0] = 1 instead22*nRC2*nRC2 = 0, BA

[1:0] = 2 instead33*nRC3*nRC2 = 1, BA[1:
[1:0] = 2 instead33*nRC3*nRC2 = 1, BA[1:0] = 3 instead44*nRC4*nRC2 = 0, BA[1:0] = 1 instead55*nRC5*nRC2 = 1, BA[1:0] = 2 instead66*nRC6*nRC2 = 0, BA[1:0] = 3 instead77*nRC7*nRC2 = 1, BA[1:0] = 0 instead88*nRC8*nRC2 = 2, BA[1:0] = 0 insteadFor x4 and x8 only99*nRC9*nRC2 = 3, BA[1:0] = 1 instead1010*nRC10*nRC2 = 2, BA[1:0] = 2 instead1111*nRC1*nRC2 = 3, BA[1:0] = 3 instead1212*nRC12*nRC2 = 2, BA[1:0] = 1 instead1313*nRC13*nRC2 = 3, BA[1:0] = 2 instead1414*nRC14*nRC2 = 2, BA[1:0] = 3 instead1515*nRC- 44 -DDR4 SDRAMRev. 1.4[ Table 39 ] IDD1, IDD1A and IPP1 Measurement-Loop PatternNumber32A[13,11]0000000000000-1, 2D, D1000000000000-3, 4D#, D#1111100007F0-...repeat pattern 1...4 until nRCD - AL - 1, truncate if necessary011010000000000D2=FF, D3=00D4=FF, D5=00...repeat pattern 1...4 until nRAS - 1, truncate if necessary0101000000000-...repeat pattern 1...4 until nRC - 1, truncate if necessary0001100100000-1*nRC + 1, 2D, D1000000000000-1*nRC + 3, 4D#, D#111110007F0-...repeat pattern nRC + 1...4 until 1*nRC + nRAS - 1, truncate if nece

ssary1*nRC + nRCD - AL01101010000D0=FF,
ssary1*nRC + nRCD - AL01101010000D0=FF, D1=00D6=FF, D7=00...repeat pattern 1...4 until nRAS - 1, truncate if necessary0101000000000-...repeat nRC + 1...4 until 2*nRC - 1, truncate if necessary22*nRC2*nRC2 = 0, BA[1:0] = 2 instead33*nRC3*nRC2 = 1, BA[1:0] = 3 instead44*nRC4*nRC2 = 0, BA[1:0] = 1 instead55*nRC5*nRC2 = 1, BA[1:0] = 2 instead66*nRC6*nRC2 = 0, BA[1:0] = 3 instead87*nRC7*nRC2 = 1, BA[1:0] = 0 instead99*nRC9*nRC2 = 2, BA[1:0] = 0 insteadFor x4 and x8 only1010*nRC10*nRC2 = 3, BA[1:0] = 1 instead1111*nRC1*nRC2 = 2, BA[1:0] = 2 instead1212*nRC12*nRC2 = 3, BA[1:0] = 3 instead1313*nRC13*nRC2 = 2, BA[1:0] = 1 instead1414*nRC14*nRC2 = 3, BA[1:0] = 2 instead1515*nRC15*nRC2 = 2, BA[1:0] = 3 instead1616*nRC- 45 -DDR4 SDRAMRev. 1.4[ Table 40 ] IDD2N, IDD2NA, IDD2NL, IDD2NG, IDD2ND, IDD2N_par, IPP2,IDD3N, IDD3NA and IDD3P Measurement-Loop PatternNumber32A[13,11]0D, D10000001D, D10000002D#, D#11111003D#, D#111110014-74-72 = 1, BA[1:0] = 1 instead28-1112 = 0, BA[1:0] = 2 instead312-1512-152 = 1, BA[1:0] = 3 instead416-1916-192 = 0

, BA[1:0] = 1 instead520-2320-232 = 1, B
, BA[1:0] = 1 instead520-2320-232 = 1, BA[1:0] = 2 instead624-2724-272 = 0, BA[1:0] = 3 instead728-3128-312 = 1, BA[1:0] = 0 instead832-3532-352 = 2, BA[1:0] = 0 instead936-3936-392 = 3, BA[1:0] = 1 instead1040-4340-432 = 2, BA[1:0] = 2 instead1144-4744-472 = 3, BA[1:0] = 3 instead1248-5148-512 = 2, BA[1:0] = 1 instead1352-5552-552 = 3, BA[1:0] = 2 instead1456-5956-592 = 2, BA[1:0] = 3 instead1560-63- 46 -DDR4 SDRAMRev. 1.4[ Table 41 ] IDD2NT and IDDQ2NT Measurement-Loop PatternNumber32A[13,11]0D, D10000001D, D10000002D#, D#11111003D#, D#111110014-74-72 = 1, BA[1:0] = 1 instead28-1112 = 0, BA[1:0] = 2 instead312-1512-152 = 1, BA[1:0] = 3 instead416-1916-192 = 0, BA[1:0] = 1 instead520-2320-232 = 1, BA[1:0] = 2 instead624-2724-272 = 0, BA[1:0] = 3 instead728-3128-312 = 1, BA[1:0] = 0 instead832-3532-352 = 2, BA[1:0] = 0 insteadFor x4 and x8 only936-3936-392 = 3, BA[1:0] = 1 instead1040-4340-432 = 2, BA[1:0] = 2 instead1144-4744-472 = 3, BA[1:0] = 3 instead1248-5148-512 = 2, BA[1:0] = 1 instead1352-5552-552 = 3, BA[1:0] = 2 inst

ead1456-5956-592 = 2, BA[1:0] = 3 instea
ead1456-5956-592 = 2, BA[1:0] = 3 instead1560-63- 47 -DDR4 SDRAMRev. 1.4[ Table 42 ] IDD4R, IDDR4RA, IDD4RB and IDDQ4R Measurement-Loop PatternNumber32A[13,11]0110100D2=FF, D3=00D4=FF, D5=001D10000002,3D#, D#11111000110100D0=FF, D1=00D6=FF, D7=005D10000006,7D#, D#111110028-1112 = 0, BA[1:0] = 2 instead312-1512-152 = 1, BA[1:0] = 3 instead416-1916-192 = 0, BA[1:0] = 1 instead520-2320-232 = 1, BA[1:0] = 2 instead624-2724-272 = 0, BA[1:0] = 3 instead728-3128-312 = 1, BA[1:0] = 0 instead832-3532-352 = 2, BA[1:0] = 0 insteadFor x4 and x8 only936-3936-392 = 3, BA[1:0] = 1 instead1040-4340-432 = 2, BA[1:0] = 2 instead1144-4744-472 = 3, BA[1:0] = 3 instead1248-5148-512 = 2, BA[1:0] = 1 instead1352-5552-552 = 3, BA[1:0] = 2 instead1456-5956-592 = 2, BA[1:0] = 3 instead1560-63- 48 -DDR4 SDRAMRev. 1.4[ Table 43 ] IDD4W, IDD4WA, IDD4WB and IDD4W_par Measurement-Loop PatternNumber32A[13,11]0110110D2=FF, D3=00D4=FF, D5=001D10000102,3D#, D#11111100110110D0=FF, D1=00D6=FF, D7=005D10000106,7D#, D#111111028-1112 = 0, BA[1:0] = 2 instead3

12-1512-152 = 1, BA[1:0] = 3 instead416-
12-1512-152 = 1, BA[1:0] = 3 instead416-1916-192 = 0, BA[1:0] = 1 instead520-2320-232 = 1, BA[1:0] = 2 instead624-2724-272 = 0, BA[1:0] = 3 instead728-3128-312 = 1, BA[1:0] = 0 instead832-3532-352 = 2, BA[1:0] = 0 insteadFor x4 and x8 only936-3936-392 = 3, BA[1:0] = 1 instead1040-4340-432 = 2, BA[1:0] = 2 instead1144-4744-472 = 3, BA[1:0] = 3 instead1248-5148-512 = 2, BA[1:0] = 1 instead1352-5552-552 = 3, BA[1:0] = 2 instead1456-5956-592 = 2, BA[1:0] = 3 instead1560-63- 49 -DDR4 SDRAMRev. 1.4[ Table 44 ] IDD4WC Measurement-Loop PatternNumber32A[13,11]D2=FF, D3=00D4=FF, D5=001,2D, D10000103,4D#, D#D0=FF, D1=00D6=FF, D7=006,7D, D10000108,9D#, D#210-1410-142 = 0, BA[1:0] = 2 instead315-1915-192 = 1, BA[1:0] = 3 instead420-2420-242 = 0, BA[1:0] = 1 instead525-2925-292 = 1, BA[1:0] = 2 instead630-3430-342 = 0, BA[1:0] = 3 instead735-3935-392 = 1, BA[1:0] = 0 instead840-4440-442 = 2, BA[1:0] = 0 insteadFor x4 and x8 only945-4945-492 = 3, BA[1:0] = 1 instead1050-5450-542 = 2, BA[1:0] = 2 instead1155-5955-592 = 3, BA[1:0] = 3 instead1

260-6460-642 = 2, BA[1:0] = 1 instead136
260-6460-642 = 2, BA[1:0] = 1 instead1365-6965-692 = 3, BA[1:0] = 2 instead1470-7470-742 = 2, BA[1:0] = 3 instead1575-79- 50 -DDR4 SDRAMRev. 1.4[ Table 45 ] IDD5B Measurement-Loop PatternNumber32A[13,11]1D10000002D10000003D#, D#4D#, D#D#, D#2 = 1, BA[1:0] = 1 instead8-1112 = 0, BA[1:0] = 2 instead12-15repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 3 instead16-19repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 1 instead20-23repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 2 instead24-27repeat pattern 1...4, use BG[1:0]2 = 0, BA[1:0] = 3 instead28-31repeat pattern 1...4, use BG[1:0]2 = 1, BA[1:0] = 0 instead32-35repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 0 insteadFor x4 and x8 only36-39repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 1 instead40-43repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 2 instead44-47repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 3 instead48-51repeat pattern 1...4, use BG[1:0]2 = 2, BA[1:0] = 1 instead52-55repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 2 instead56-59repeat pattern 1.

..4, use BG[1:0]2 = 2, BA[1:0] = 3 inste
..4, use BG[1:0]2 = 2, BA[1:0] = 3 instead60-63repeat pattern 1...4, use BG[1:0]2 = 3, BA[1:0] = 0 instead264 ... nRFC - 1repeat Sub-Loop 1, Truncate, if necessary- 51 -DDR4 SDRAMRev. 1.4[ Table 46 ] IDD7 Measurement-Loop PatternNumber32A[13,11]D2=FF, D3=00D4=FF, D5=002D10000003D#1111100... �repeat pattern 2...3 until nRRD - 1, if nRRD 4. Truncate if necessaryD0=FF, D1=00D6=FF, D7=00... �repeat pattern 2 ... 3 until 2*nRRD - 1, if nRRD 4. Truncate if necessary22*nRRD2*nRRD2 = 0, BA[1:0] = 2 instead33*nRRD3*nRRD2 = 1, BA[1:0] = 3 instead44*nRRDrepeat pattern 2 ... 3 until nFAW - 1, if nFAW� 4*nRRD. Truncate if necessary5nFAWW2 = 0, BA[1:0] = 1 instead6nFAW + nRRDW + nRRD2 = 1, BA[1:0] = 2 instead7nFAW + 2*nRRDW + 2*nRRD2 = 0, BA[1:0] = 3 instead8nFAW + 3*nRRDW + 3*nRRD2 = 1, BA[1:0] = 0 instead9nFAW + 4*nRRDrepeat Sub-Loop 4102*nFAWW2 = 2, BA[1:0] = 0 insteadFor x4 and x8 only112*nFAW + nRRD + nRRD2 = 3, BA[1:0] = 1 instead122*nFAW + 2*nRRD + 2*nRRD2 = 2, BA[1:0] = 2 instead132*nFAW + 3*nRRD + 3*nRRD2 =

3, BA[1:0] = 3 instead142*nFAW + 4*nRRDr
3, BA[1:0] = 3 instead142*nFAW + 4*nRRDrepeat Sub-Loop 4153*nFAWW2 = 2, BA[1:0] = 1 instead163*nFAW + nRRD + nRRD2 = 3, BA[1:0] = 2 instead173*nFAW + 2*nRRD + 2*nRRD2 = 2, BA[1:0] = 3 instead183*nFAW + 3*nRRD + 3*nRRD2 = 3, BA[1:0] = 0 instead193*nFAW + 4*nRRDrepeat Sub-Loop 4204*nFAW�repeat pattern 2 ... 3 until nRC - 1, if nRC 4*nFAW. Truncate if necessary- 52 -DDR4 SDRAMRev. 1.411.2 4Gb DDR4 SDRAM E-die IDD Specification Table[ Table 47 ] 3535TBDmA3637TBDmA5353TBDmA5556TBDmA1515TBDmA1818TBDmA1616TBDmA1111TBDmA1515TBDmA1212TBDmA1515TBDmA1010TBDmA1313TBDmA2727TBDmA2828TBDmA1313TBDmA118129TBDmA122133TBDmA121133TBDmA8786TBDmA91100TBDmA8796TBDmA8083TBDmA93103TBDmA194195TBDmA160160TBDmA120120TBDmA1313TBDmA2020TBDmA1010TBDmA1313TBDmA185186TBDmA6.56.5TBDmA- 53 -DDR4 SDRAMRev. 1.4[ Table 48 ] [ Table 49 ] 3. Applicable for MR2 settings A6=0 and A7=0.5. Applicable for MR2 settings A6=0 and A7=1. I is only specified for devices which support the Extended Temperature Range feature.44TBDmA44TBDmA33TBDmA33TBDmA33TBDmA33TBDmA33TB

DmA33TBDmA1919TBDmA1616TBDmA1212TBDmA44T
DmA33TBDmA1919TBDmA1616TBDmA1212TBDmA44TBDmA44TBDmA44TBDmA44TBDmA1212TBDmA22TBDmATemperature RangeValueC1313TBDmA3,4C2020TBDmA4,5- 54 -DDR4 SDRAMRev. 1.412. Input/Output Capacitance[ Table 50 ] Silicon pad I/O CapacitanceInput/output capacitance 0.551.40.551.15pF 1,2,3Input/output capacitance delta -0.10.1-0.10.1pF 1,2,3,11-0.05-0.05pF Input capacitance, CK_t and CK_c0.20.80.20.7pF Input capacitance delta CK_t and CK_c-0.05-0.05pF 0.20.80.20.7pF Input capacitance delta(All CTRL pins only) -0.10.1-0.10.1pF -0.10.1-0.10.1pF Input/output capacitance of ALERT 0.51.50.51.5pF Input/output capacitance of ZQ 0.52.30.52.3pF Input capacitance of TEN 0.22.30.22.3pF 1,3,13- 55 -DDR4 SDRAMRev. 1.4[ Table 51 ] DRAM package electrical specifications(X16)Input/output Zpkg 4585Input/output Pkg Delay 1445psInput/Output Lpkg-3.4nH 1, 2Input/Output Cpkg-0.82pF 1, 3DQS_t, DQS_c Zpkg 4585DQS_t, DQS_c Pkg Delay 1445psDQS Lpkg-3.4nH 1, 2DQS Cpkg-0.82pF 1, 3Delta Zpkg DQSU_t, DQSU_c-10Delta Zpkg DQSL_t, DQSL_c-10Delta Delay DQSU_t, DQSU_c-5ps-Delt

a Delay DQSL_t, DQSL_c-5ps-Input CTRL pi
a Delay DQSL_t, DQSL_c-5ps-Input CTRL pins Zpkg 5090Input CTRL pins Pkg Delay 1442psInput CTRL Lpkg-3.4nH 1, 2Input CTRL Cpkg-0.7pF 1, 3Input- CMD ADD pins Zpkg 5090Input- CMD ADD pins Pkg Delay 1452psInput CMD ADD Lpkg-3.9nH 1, 2Input CMD ADD Cpkg-0.86pF 1, 3CLK_c Zpkg 5090CLK_c Pkg Delay 1442psInput CLK Lpkg-3.4nH 1, 2Input CLK Cpkg-0.7pF 1, 3Delta Zpkg CLK_c -10Delta Delay CLK_c -5psZQ Zpkg 36100ZQ Delay 2090psALERT Zpkg 40100ALERT Delay 2055ps- 56 -DDR4 SDRAMRev. 1.413. Electrical Characteristics & AC Timing 13.1 Reference Load for AC Timing and Output Slew Rate 23Figure 23. Reference Load for AC Timing and Output Slew Rate13.2 tREFI Average periodic Refresh interval (tREFI) of DDR4 SDRAM is defined as shown in the table.[ Table 52 ] tREFI by device density2. Supported only for Industrial TemperatureAverage periodic refresh interval7.87.87.8sCTCASE 85Cs3.93.93.9sTiming Reference PointTiming Reference Point- 57 -DDR4 SDRAMRev. 1.413.3 Timing Parameters by Speed Grade[ Table 53 ] Timing Parameters by Speed B

in for DDR4-1600 to DDR4-26668208208208
in for DDR4-1600 to DDR4-2666820820820820820ns -Average Clock Period tCK(avg) 1.251.0710.9380.8330.750ns35,36Average high pulse width tCH(avg) 0.480.520.480.520.480.520.480.520.480.52tCK(avg) Average low pulse width tCL(avg) 0.480.520.480.520.480.520.480.520.480.52tCK(avg) Absolute Clock Period tCK(abs) Absolute clock HIGH pulse width tCH(abs) 0.45 -0.45 -0.45 -0.45 -0.45-tCK(avg) 23Absolute clock LOW pulse width tCL(abs) 0.45 -0.45 -0.45 -0.45 -0.45-tCK(avg) 24Clock Period Jitter- total JIT(per)_tot -6363-5454-4747 -4242-3838ps23Clock Period Jitter- deterministic JIT(per)_dj -3131-2727-2323-2121-1919ps26tJIT(per, lck) -5050-4343-3838-3333-3030psCycle to Cycle Period Jitter tJIT(cc)_total -125-107-94-83-75ps25Cycle to Cycle Period Jitter deterministic tJIT(cc)_dj -63-54-47-42-38ps26tJIT(cc, lck) -100-86-75-67-60psDuty Cycle Jitter tJIT(duty) TBDTBDTBDTBDTBDTBDTBDTBDTBDTBDpsCumulative error across 2 cycles tERR(2per) -9292-7979-6969-6161-5555psCumulative error across 3 cycles tERR(3per) -109109-9494-8282-7373-6666psCumulative error a

cross 4 cycles tERR(4per) -121121-104104
cross 4 cycles tERR(4per) -121121-104104-9191-8181-7373psCumulative error across 5 cycles tERR(5per) -131131-112112-9898-8787-7878psCumulative error across 6 cycles tERR(6per) -139139-119119-104104-9292-8383psCumulative error across 7 cycles tERR(7per) -145145-124124-109109-9797-8787psCumulative error across 8 cycles tERR(8per) -151151-129129-113113-101101-9191psCumulative error across 9 cycles tERR(9per) -156156-134134-117117-104104-9494psCumulative error across 10 cycles tERR(10per) -160160-137137-120120-107107-9696psCumulative error across 11 cycles tERR(11per) -164164-141141-123123-110110-9999psCumulative error across 12 cycles tERR(12per) -168168-144144-126126-112112-101101psCumulative error across 13 cycles tERR(13per) -172172-147147-129129-114114-103103psCumulative error across 14 cycles tERR(14per) -175175-150150-131131-116116-104104psCumulative error across 15 cycles tERR(15per) -178178-152152-133133-118118-106106psCumulative error across 16 cycles tERR(16per) -180189-155155-135135-120120-108108psCumulative error across 17 c

ycles tERR(17per) -183183-157157-137137-
ycles tERR(17per) -183183-157157-137137-122122-110110psCumulative error across 18 cycles tERR(18per) -185185-159159-139139-124124-112112psCommand and Address setup time to CK_c referenced to Vih(ac) / Vil(ac) levelstIS(base)115-100-80-62-TBD-psCommand and Address setup time to CK_c referenced to Vref levelstIS(Vref)215-200-180-162-TBD-psCommand and Address hold time to CK_t,CK_c referenced to Vih(dc) / Vil(dc) levelstIH(base)140-125-105-87-TBD-psCommand and Address hold time to CK_t,CK_c referenced to Vref levelstIH(Vref)215-200-180-162-TBD-psControl and Address Input pulse width for tIPW600-525-460-410-385-psCommand and Address Timing-nCK34CAS_n to CAS_n command delay for differ-tCCD_S4-4-4-4-4-nCK34ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size-nCK34ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size-nCK34- 58 -DDR4 SDRAMRev. 1.4ACTIVATE to ACTIVATE Command delay to different bank group for 1/2KB page size-nCK34ACTIVATE to ACTIVATE Command delay -nCK34ACTIVATE to ACTIVATE Co

mmand delay -nCK34ACTIVATE to ACTIVATE C
mmand delay -nCK34ACTIVATE to ACTIVATE Command delay -nCK34Four activate window for 2KB page sizetFAW_2K-ns34Four activate window for 1KB page sizetFAW_1K-ns34Four activate window for 1/2KB page sizetFAW_1/2K-ns34to internal read command for different bank -ns-ns1,34tRTP-ns34WRITE recovery timetWR15-15-15-15-15-ns1-ns1, 28-ns-nsDLL locking timetDLLK597-597-768-768-854-nCKMode Register Set command cycle timetMRD8-8-8-8-8-nCKMode Register Set command update delaytMOD-nCKMulti-Purpose Register Recovery TimetMPRR1-1-1-1-1-nCK33Multi Purpose Register Write Recovery Time + AL + PL+ AL + PL+ AL + PL+ AL + PL+ AL + PL-nCKtDAL(min)Programmed WR + roundup ( tRP / tCK(avg)) nCKtPDA_S 0.5 -0.5 -0.5 -0.5 -0.5-UI45,47tPDA_H 0.5 -0.5 -0.5 -0.5 -0.5-UI46,47CS_n to Command Address LatencyCS_n to Command Address LatencytCAL3-4-4--nCKMode Register Set cyce time in CAL mode tMRD_tCAL -nCK-nCKDRAM Data TimingDQS_t,DQS_c to DQ skew, per group, per tDQSQ-0.16-0.16-0.16-0.16-0.18tQH0.76-0.76-0.76-0.74-0.74-0.63-0.63-0.64-0.64-TBD-9,49Data Valid Win

dow , per pin per UI : (tQH - tDQSQ) eac
dow , per pin per UI : (tQH - tDQSQ) each UI on a pin of a given DRAM0.66-0.66-0.69-0.72-0.72-9,49-450225-390195-390180DQ high impedance time from CK_t, CK_c tHZ(DQ) -225-195-180175-Data Strobe Timing- 59 -DDR4 SDRAMRev. 1.4DQS_t, DQS_c differential READ Preamble tRPRE0.9NOTE440.9NOTE440.9tCK39,40NANANANANANA1.8tCK39,41DQS_t, DQS_c differential READ Postam-tRPST0.33NOTE 450.33NOTE 450.33tCK39DQS_t,DQS_c differential output high timetQSH0.4-0.4-0.4-0.4-0.4-tCK21,39DQS_t,DQS_c differential output low timetQSL0.4-0.4-0.4-0.4-0.4-tCK20,39DQS_t, DQS_c differential WRITE Pream-0.9-0.9-0.9-0.9-0.9-tCK42NANANA1.8-1.8-tCK43DQS_t, DQS_c differential WRITE Postam-tWPST0.33-0.33-0.33-0.33-0.33-tCKtLZ(DQS)-450225-390195-360180-330175-310170ps39tHZ(DQS)-225-195-180-175-170ps39DQS_t, DQS_c differential input low pulse tDQSL0.460.540.460.540.460.540.460.540.460.54tCKDQS_t, DQS_c differential input high pulse tDQSH0.460.540.460.540.460.540.460.540.460.54tCKtDQSS-0.270.27-0.270.27-0.270.27-0.270.27-0.270.27tCKtDSS0.18-0.18-0.18-0.18-0

.18-tCKtDSH0.18-0.18-0.18-0.18-0.18-tCK-
.18-tCKtDSH0.18-0.18-0.18-0.18-0.18-tCK-225225-195195-180180-175175-170170ps-370-330-310-290-270psMPSM Timing-TBD-Valid clock requirement after MPSM entrytCKMPE-TBD-Valid clock requirement before MPSM exittCKMPX-TBD-tXMPtXS(min)-tXS(min)-tXS(min)-tXS(min)-TBD--TBD-CS setup time to CKEtMPX_S-TBD-Calibration TimingPower-up and RESET calibration timetZQinit1024-1024-1024-1024-1024-nCKNormal operation Full calibration timetZQoper512-512-512-512-512-nCKNormal operation Short calibration timetZQCS128-128-128-128-128-nCKReset/Self Refresh Timing-nCK-nCKDLL in Self Refresh ABORTS_ABORT(min-nCK(CL,CWL,WR,RTP and Gear Down)tXS_FAST -nCK-nCK-nCK- 60 -DDR4 SDRAMRev. 1.4tCKESR_ PAR-nCKValid Clock Requirement after Self Refresh -nCKValid Clock Requirement after Self Refresh tCKSRE_PAR-nCKValid Clock Requirement before Self Re--nCKPower Down Timing-nCKCKE minimum pulse widthtCKE-nCK31,32Command pass disable delaytCPDED4-4-4-4-4-nCKPower Down Entry to Exit TimingtPD9*tREFInCK6Timing of ACT command to Power Down tACTPDEN1-1-2-2-2-nCK7Timing of

PRE or PREA command to Power tPRPDEN1-1-
PRE or PREA command to Power tPRPDEN1-1-2-2-2-nCK7Timing of RD/RDA command to Power tRDPDENRL+4+1-RL+4+1-RL+4+1-RL+4+1-RL+4+1-nCKTiming of WR command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)-nCK4Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BC4OTF)-nCK5Timing of WR command to Power Down -nCK4Timing of WRA command to Power Down -nCK5Timing of REF command to Power Down tREFPDEN1-1-2-2-2-nCK7Timing of MRS command to Power Down -nCKPDA Timing-nCKtMOD_PDAtMODtMODtMODtMODtMODnCK ODT TimingAsynchronous RTT turn-on delay (Power-tAONAS1.09.01.09.01.09.01.09.01.09.0nsAsynchronous RTT turn-off delay (Power-tAOFAS1.09.01.09.01.09.01.09.01.09.0nsRTT dynamic change skewtADC0.30.70.30.70.30.70.30.70.30.7tCK(avg) Write Leveling TimingtWLMRD40-40-40-40-40-nCK12tWLDQSEN25-25-25-25-25-nCK12Write leveling setup time from rising CK_t, tWLS0.13-0.13-0.13-0.13-0.13-tCK(avg)Write leveling hold time from rising DQS_t/-0.13-Write leveling output delay9.509.5Write leveling output errortWLOE0202020202nsCA Parity Timing tPAR_UN--PL-PL-PL

-PL-PLnCK- 61 -DDR4 SDRAMRev. 1.4Delay
-PL-PLnCK- 61 -DDR4 SDRAMRev. 1.4Delay from errant command to ALERT_n tPAR_ALERT_-PL+6nsPulse width of ALERT_n signal when as-tPAR_ALERT_489656112641287214480160nCK_RSP 64-Parity Latency CRC error to ALERT_n latencytCRC_ALERT13313CRC ALERT_n pulse widthCRC_ALERT_10610Exit RESET from CKE HIGH to a valid MRS geardown (T2/Reset) TBDTBDR TBDSync pulse to First valid command(T4) TBDGeardown setup time 2Geardown hold time 22Gb160-160-160-160-160-ns344Gb260-260-260-260-260-ns348Gb350-350-350-350-350-ns3416GbTBD-TBD-TBD-550-550-ns342Gb110-110-110-110-110-ns344Gb160-160-160-160-160-ns348Gb260-260-260-260-260-ns3416GbTBD-TBD-TBD-350-350-ns342Gb90-90-90-90-90-ns344Gb110-110-110-110-110-ns348Gb160-160-160-160-160-ns3416GbTBD-TBD-TBD-260-260-ns34- 62 -DDR4 SDRAMRev. 1.4. 1.4()ming all input clock jitterspecifications are satisfied9. When CRC and DM are both enabled, tWR_CRC_DM is used in place of tWR.10. When CRC and DM are both enabled tWTR_S_CRC_DM is used in place of tWTR_S.11. When CRC and DM are both e

nabled tWTR_L_CRC_DM is used in place of
nabled tWTR_L_CRC_DM is used in place of tWTR_L.12. The max values are system dependent.13. DQ to DQS total timing per group where the total includes the sum of deterministic and random timing terms for a specified BER. BER spec and measurement method are tbd.14. The deterministic component of the total timing. Measurement method tbd.15. DQ to DQ static offset relative to strobe per group. Measurement method tbd.16. This parameter will be characterized and guaranteed by design.17U When the device is operated with the input clock jitter, this parameter needs to be derated by the actual tjit(per)_total of toximately 0.7 * VDDQ as a center level of the - 63 -DDR4 SDRAMRev. 1.413.4 The DQ input receiver compliance mask for voltage and timingThe DQ input receiver compliance mask for voltage and timing is shown in the figure below. The receiver mask (Rx Mask) defines Figure 24. DQ Receiver(Rx) compliance maskFigure 25. Across pin Vref DQ voltage variationThe Vref_DQ voltage is an internal reference voltage level that shall be set to

the properly trained setting, which is
the properly trained setting, which is generallVcent_DQ is defined as the midpoint between the largest Vref_DQ voltage level and the smallest Vref_DQ voltage level across allDDR4 DRAM component. Each DQ pin Vref level is defined by the center, i.e. widest opening, of the cumulative data input eye as 24.This clarifies that any DDR4 DRAM component level variation must be accounted for within the DDR4 DRAM Rx mask.The componenVref will be set by the system to account for Ron and ODT settings.Vcent_DQxVcent_DQyVref variation(Smallest Vref_DQ Level)(Largest Vref_DQ Level)- 64 -DDR4 SDRAMRev. 1.4Figure 26. DQS to DQ and DQ to DQ Timings at DRAM Balls 26 are measured at the VdIVW_total voltage levels centered around Vcent_DQ(midpoint) and are referenced to the DQS_tDQS_cDQS_t0.5xTdiVW0.5xTdiVWTdiVWDQS, DQs Data-in at DRAM BallRx MaskRx Mask - Alternative ViewVdiVW0.5xTdiVW0.5xTdiVWTdiVWDQx-zDRAMaVdiVWtDQS2DQtDQ2DQDQyDRAMbVdiVWDQzDRAMbVdiVWtDQS2DQtDQ2DQDQzDRAMcVdiVWDQyDRAMcVdiVW+ 0.5 x TdiVWtDQ2DQDQyDRAMbVdiVWDQ

zDRAMbVdiVW+ 0.5 x TdiVWDQzDRAMcVdiVW
zDRAMbVdiVW+ 0.5 x TdiVWDQzDRAMcVdiVWDQyDRAMcVdiVWTdiVWtDQ2DQRx MaskTdiVWRx MaskTdiVWRx MaskTdiVWtDQ2DQ TdiPW is not shown; composite data-eyes shown would violate TdiPW. VCENT DQ(midpoint) is not shown but is assummed to be midpoint of VdiVW.. - 65 -DDR4 SDRAMRev. 1.4The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in Figure 5A below: A low to high Figure 27. Slew Rate Conditions For Rising TransitionThe falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in Figure 5B below: A high to low Figure 28. Slew Rate Conditions For Falling Transition0.5*VHL_AC(min)0.5*VHL_AC(min)0.5*VdiVW(max)0.5*VdiVW(max)Vcent_DQ(midpoint)VdiVW(max)0.5*VHL_AC(min)0.5*VHL_AC(min)0.5*VdiVW(max)0.5*VdiVW(max)Vcent_DQ(midpoint)VdiVW(max)- 66 -DDR4 SDRAMRev. 1.4[ Table 54 ] DRAM DQs In Receive Mode; edge must be within 1.7 V/ns of each other. VdIVWRx Mask voltage - pk-pk --130-120mV1,2

,10TdIVWRx timing window --0.2-0.22UI*1
,10TdIVWRx timing window --0.2-0.22UI*1,2,10VIHL_ACDQ AC input swing pk-pk186-160-150-mV 3,4,10TdIPWDQ input pulse width0.580.580.58-UI* 5,10tDQS2DQRx Mask DQS to DQ offset-0.170.17-0.170.17-0.190.19UI*6, 10tDQ2DQRx Mask DQ to DQ offset-tbd-tbd-0.105UI*7�Input Slew Rate over VdIVW if tCK = 0.935ns1.091.091.0tbdV/ns8,10--1.2591.25tbdV/ns8,100.2*srr190.2*srr190.2*srr1tbdV/ns9,100.2*srf190.2*srf190.2*srr1tbdV/ns9,10- 67 -DDR4 SDRAMRev. 1.413.5 DDR4 Function MatrixDDR4 SDRAM has several features supported by ORG and also by Speed. The following Table is the summary of the features.[ Table 55 ] Function Matrix (By ORG. V:Supported, Blank:Not supported)Write LevelingTemperature controlled RefreshLow Power Auto Self RefreshDQ Vref TrainingPer DRAM Addressability- 68 -DDR4 SDRAMRev. 1.4[ Table 56 ] Function Matrix (By Speed. V:Supported, Blank:Not supported)than250MbpsMbpsWrite LevelingVVVVTemperature controlled RefreshVVVVLow Power Auto Self RefreshVVVVVVVVVVVVVVVVVVVVVVVVVVVDQ Vref TrainingVVVVPer DRAM AddressabilityVVVVV