1 F Anghinolfi 080213 Introduction What we present today A set of responses to the previous review report see next slides and other talks Updated information about the ABC130 frontend from updated detector parameters after irradiation ID: 802336
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Slide1
ABC130
08 February 2013
ABC 130 Final Design Review
1
F. Anghinolfi
08/02/13
Slide2Introduction
What we present today :
A set of responses to the previous review report (see next slides and other talks)
Updated information about the ABC130 front-end (from updated detector parameters after irradiation)
Voltage regulators setup and power up case
Verification processes
Near “final” layout figures
Some open questions, that may impact the submission scheduleMost probable submission scenariosFirst evaluations test proposal
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Slide3Introduction
The ABC130 design team
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F
.
Anghinolfi
08/02/13
PENNMitch NewcomerSystem, specs, overviewNandor Dressnandt
IO designs, shunt device
Amogh HalgheriInput
registers,
FastClusterFinder
Michal
Bochenek
Voltage
RegulatorRALMichelle Key-CharriereFunctional VerificationGeneva UniversityDaniel La MarraL1-DCL, Top Logic designSanta CruzJoel de Witt Command decoder, registers, readout and serializer
Krakow
Krzysztof
Swientek
Encounter, final DRC and
LVS
CERN
Francis
Anghinolfi
Pipeline and buffers, verifications
Jan
Kaplon
Front-End design
Piotr
Rymaszewski
FE
layout, power up simulations
Filipe Sousa
TMR insertion
C.
Paillard
SRAM
design
David
Monzat
SRAM
layout and
charact
.
Bruno
Allongue
SRAM
SEU cross section
UCL
Samer
Kilani
R3-DCL
Slide4Main Progresses
since last review
ABC130 :
RTL code completion (but not frozen actually)
ABC ID chip address field moved from 4 to 5 bits (60 bits readout packet)
Adding a 5 bits HCC ID field address to the commands packets (58 bits readout packets instead of 54)
New
definition of the command packet to include the HCC commands(at HCC output) : 64 bits packet size, 2 scrambling options (one is 8b/10b that extends the packet size to 80 bits)4F. Anghinolfi08/02/13
Slide5Main Progresses
since last review
ABC130 :“What
are required operating margins: clock frequencies, cluster search time, trigger rates, data transmission FIFO depth, etc.?”
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Clock FrequenciesSimulation 41.7MHz/166MHz
Cluster
Search TimeR3 : 4BC (100ns)
L1 : 64BC (1.6us)
Trigger Rates
Simulation
1MHz L0/50KHz R3/200KHz L1
BW limit is reached if packets > 2 per L1
Trigger (6 clusters)FIFO depthsThru aCSRL1R3bCSR4864168XOFF stops transferRequired for “all hits @ 1”
Slide6Main Progresses
since last review
ABC130 :
“Some of the designs show some degree of "committeeization
", that is there was a lack of coherence in some cases between design approaches to related problems - for instance in having multiple data compression algorithms or multiple
bandgap
designs
“BANDGAP : Only one version (3 copies) used in ABC130.Data Compression Algorithm : difference is justified by 1) execution time 2) limited data per event per chip for R3 (one packet only), full data per event per chip for L1 (up to 24 packets) 6F. Anghinolfi08/02/13
Slide7Main Progresses
since last review
ABC130 :“The
simulation test bench presented is an excellent tool, and it should be exploited to its fullest extent. An effort should be made by the strip community to document all operation use cases, both for normal operations and exceptions, and these should then be implemented as test bench vectors. All vectors should eventually be run on the final design with timing back-
annotation”
See status during the presentation on functional verification
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Slide8Main Progresses
since last review
ABC130 :“Models
for analog blocks could be produced and included in the test bench simulation. These can be simple models that simply provide dummy values or use register data in dummy ways, or more sophisticated depending on available resourced and usefulness of more sophistication
.”Most of the analogue blocks have a functional model where the activity is
displayed during functional verification
(Regulator ON/OFF, FE block bias change,
etc ….)8F. Anghinolfi08/02/13
Slide9Main Progresses
since last review
ABC130 :“One
of the SEU mitigation techniques will be a “watchdog” circuit in the data compression logic to provide a reset if the logic should ever become hung-up. While this technique can resolve such SEU created problems, they can sometime cause their own problems by incorrectly over reacting. The triplication protection of the watchdog circuit should be carefully studied so that its sensitivity is well understood. Francis during the
review”
The
watchdogs
are triplicated and used only on the DCL functions. The watchdog can only corrupt the DCL function (ie one packet or serie of packet formation) but not the entire chip.9F. Anghinolfi08/02/13
Slide10ABC130 Physical layout Main Progresses :
ABCN:
I/O definition (double size pads), ESD protection devices, and power distribution
Pad ring definition and pads physical layout
Physical layout : Front-End (completed) custom layout
Back-end and chip assembly through Encounter (timing constraints are always part of the chip assembly)
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F. Anghinolfi08/02/13
Slide11IRRADIATIONS
RAM block SEU cross section has been measured at
H4IRRAD (Mixed field) from 15 Nov to 3
rd Dec, total
fluence
2.
5E11HEH
/cm2 : cross section 4.8E-14SEU : ABC 130 in its first version WILL NOT BE “FULLY” protected against SEU errors : a specific/serious program for evaluating the SEU risk should be prepared (resource, money) to run tests with the ABC130 (&HCC) coming versions.11F. Anghinolfi08/02/13
Slide12ABC130 Assembly : The
Front_End
The Front-End block shows the input (to strip) pads area (on left) then the active area elements (256 channels, center) then in green the power bus bars extending at right to connect to the Analogue power pads across the Digital block
On top 2 pads are placed for test purpose
FE block size (without power bars extension over the Digital block )
7862 um x 2615 um
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Slide13ABC130 Assembly : Digital Block (BE)
Pads ring as agreed with hybrid designers (Ashley,
Nobu
etc ..)
Pipeline RAMs
Analogue power regulator
Shunt Devices (Serial Power)
Pipeline RAMs
Central part has most of the standard cells logic and will be covered by the analogue power bus extension
R3L1 Buffers
BE
block
size
7900
um x
4000
um
Digital power regulator
R3L1 Buffers
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Slide14ABC130 Assembly : Preliminary view
Chip size
7900
um x 6700 um
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Slide15ABC130 Current Status
Actual :
Assembly of FE and BE (Krzysztof (layout)/Francis(functional))Encounter : layout verification (DRC, LVS through Calibre and Assura
)Next :
Functional verification with delay annotations
F. Anghinolfi
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Slide16Elements discussed by designers
FastClusterFinder
layout implementation is not done and can be seen as one block delaying the expected submission timeDigital power estimates (from tools) are poor
: our confidence in numbers is low.
eFUSE register implementation adds special constraints : do we need it on this version ?
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