Valerio and Edinei Santin CLICdp Vertex Meeting August 12 th 2015 Digital Design Part Pierpaolo Valerio Suggestions from the DR Packet format change SPI interface DAC resetread ID: 788725
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Slide1
CLICpix2 Design Status
Pierpaolo
Valerio and Edinei Santin
CLICdp
Vertex Meeting -
August 12
th
2015
Slide2Digital Design Part
Pierpaolo
Valerio
Slide3Suggestions from the DR
Packet format change
SPI interface
DAC reset/read
Enable signal for Power Pulsing
Automatic Test Pulse generatorPRBS generatorToA Validation with full column simulation
3
Slide4Ethernet packet encapsulation
As suggested, now the
datastream
is properly divided into packets, each containing data from a double column
The idle pattern for synchronization complies with the Ethernet specifications
These modifications should make the data format much more easily readable4
Slide5More standard SPI interface
The SPI interface now always works with a 8bit address + 8bit data format
Every time data is written in a configuration register, old data is shifted out for debug purposes
5
CS
DATA_IN
DATA_OUT
address
data
data
Slide6New programming algorithm
Using the SPI interface, matrix programming is now done using a standard command, 8 bits at a
time
This makes implementing the DAQ firmware easier, but it comes at the cost of additional overhead when performing the programming routine
6
Slide7PRBS for link testing
There is now a command to have the chip send a sequence of pseudo-random data to test the error rate of the link between the chip and the
DAQ
The same command stops the data
stream
The sequence is periodic with a very long period (65k words)
7
Slide8Automatic Test-Pulse generator
The chip can now be programmed to generate a sequence of test pulses automatically
Both the number of pulses and the delay between them can be programmed independently; enough test pulses can be produced to saturate the 13-bit event counter
It is still possible to use an external trigger if needed
8
Slide9Other features
DACs are now reset at the nominal values when the global reset signal is asserted
It is possible to disable the power pulsing with a configuration option
The power pulsing logic will still be used, but the biasing lines will not be switched
9
Slide10Full column
ToA
simulation
A full column was simulated with a fully extracted digital model and a simplified analog model to check for the validity of the
ToA
measurementsThe analog pixel has “realistic” noise and mismatch modelsSending a pulse to all pixels at the same time, the expected behavior is to have two different
ToA
results (due to the
unknown
phase of the input pulse related to the clock)
10
Slide11Full column
ToA
simulation
1000 test pulses were injected with random arrival and shutter times in the simulation
Without noise and mismatch the
ToA had no errors (only two values are recorded)With noise and mismatch, we have an error rate of
~0.013%
11
Slide12Things left to do
Check the feasibility of the
fastor
signal
Code cleanup
Some minor suggestions made during the code review need to be implementedSimulation of the interface with the DAQPlacing DDR bufferSynthesis of the peripherySimulation of extracted periphery + pixel matrix
12
Slide13Analog Design Part
Edinei Santin
Slide14DR points covered here
Further verification of the frontend in terms of
PSRR
and
stability
/noise wrt to leakage current and input capacitance
Verification of the
output swing
of the comparator
New topology for the
calibration DAC
Crosstalk
between pixels
14
Slide15PSRR definition
For both
V
dd
and
Vss, the PSRR is defined as the inverse of the transfer function from the specific rail to the output. Hence, the higher the PSRR, the better the circuit is in rejecting noise from the supply/ground lines.15
Slide16PSRRdd &
PSRR
ss
(
xRC)For most of the spectrum, PSRRss is worst than PSRRddPSRR degradation is mainly caused by the devices
M
in
and
M
load
(see previous slide)
Example: A ripple of
1 mV
at
~3
MHz
on the Vss line will cause
~17 mV at the CSA output pay particular attention on the power supplies design
16
Slide17Ileak &
C
in
effects on FE stability (
xRC
)Stability verified in time domain to avoid ambiguous loop gain frequency response (i.e. non-monotonic phase)Overshoot varies
< 1.5%
for a wide range of
I
leak
/
C
in
values
small impact on FE stability
Settling time
is almost independent of
I
leak
17Holes collection mode; Qin = 5 ke-
Slide18Ileak &
C
in
effects
on FE noise (
xRC)Input-referred noise increases considerably with Cin, but it’s almost independent of Ileak The noisier devices are
M
in
(27.5%),
M
1a
(15.6%), and
M
2
(13.5%), i.e., the ones connected to the input node of the CSA
Noise spec (
70e-
) is fulfilled for C
in < ~30 fF
18
Slide19Comparator output swing
19
Comparator core and inverter at different power domains:
V
dda
= 1.2V and Vddd = 1.0VQuestion: Is the output swing of the comparator enough to drive the CMOS inverter following it if
V
ddd
is increased to 1.2V (e.g. to use a single power supply)?
Slide20Comparator swing vs Qin (
xRC
)
Well-defined output states for Q
in
> ~600 e- the output swing of the comparator is large enough to properly drive the CMOS inverter powered at 1.2VMaximum output swing of the comparator is ~1V
20
comp diff in
comp out
inv
out
Slide21Rafa’s
cal. DAC topology
Rafa’s
topology covers
15I
lsb differentially while the original one covers
28I
lsb
. Hence, the
I
lsb
value must be
doubled
to span the same range.
Power dissipation
keeps the same because current sources are more or less halved
Area
of the current sources
is roughly reduced by a factor of two
21Original topologyRafa’s topology
Slide22Cal. DAC correction limits (xRC)
6
σ
FE spread
is ~50mV Ilsb,nom ~25nA (original) and ~50nA (
Rafa
)
INL is better than
0.5 LSB
for
I
lsb
as large as twice the required value for both topologies
22
Original topology
Rafa’s
topology
Slide23Cal. DAC mismatch (xRC)
100-case MC
analyses show the INLs of the cal. DACs are always within 0.5 LSB
The
worst-case INL
is 0.32 LSB (original) and 0.30 LSB (Rafa’s topology). That is, both topologies have similar performance in terms of matching with the same transistors
sizing
23
Original topology
Rafa’s
topology
Slide24New FE layout
24
Previous layout
New layout
Slide25Crosstalk between pixels
Two
superpixels
have been extracted to accurately represent inter-pixel neighborhoods
To achieve a manageable extracted netlist, only C+CC
parasitics have been extractedPixel 1 excited and crosstalk observed in pixels 2 to 5Input clock of the digital circuitry running at 100 MHz Also taken into account: analog/digital V
dd
/
V
ss
modeling
(next
slide),
parasitic diodes
, and
multiple ground regions
25
Slide26Power/ground lines modeling
26
Simple model contemplates
bond wire inductance
(
L
b
),
series resistance
(
R
s
), and on-chip
bypass capacitance
(
C
byp
)
Typical values (coarse approximation) for
Lb
, Rs, and C
byp are indicated
Slide27Crosstalk at the input of the comparators (
xRC
)
27
Maximum error due to crosstalk is ~0.5 mV (
15e-
) which is ~5x lower than the noise spec (
70e-
)
1
2
4
3
5
~41mV
Slide28To-do list
Improve the design of the periphery DAC
buffers
Add
cascode
current mirrors in the periphery DACs to enhance their linearityIncrease the resolution of the periphery ‘test pulse’ DAC
and do a
full simulation
of the test pulse circuitry
Reduce the
I
krum
tuning range
by changing the current mirror
ratio
in the corresponding periphery DAC
Integrate the
bandgap
blockFinal chip assembly and
verification28
Slide29Thank you!
Slide30Backup slides
Slide31Parasitic diodes extraction
31
Rules file has two “switches” to enable the
extraction of parasitic diodes
(they aren’t extracted by default!)
Example of extracted diodes
Slide32Multiple ground regions (1/3)
32
The
parasitics
extraction software used (
Calibre
) has a way to define multiple ground regions (VSSA and VSSD in this example). Hence, the extracted intrinsic capacitances are referenced to the appropriate ground.
Slide33Multiple ground regions (2/3)
33
Slide34Multiple ground regions (3/3)
34
Example of extracted parasitic capacitances without and with multiple ground regions definition