Andrew B Kahng Seokhyeong Kang Hyein Lee Siddhartha Nath and Jyoti Wadhwani VLSI CAD LABORATORY UC San Diego 15 th ACMIEEE SystemLevel Interconnect Prediction Workshop June 2 nd 2013 ID: 404368
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Slide1
Learning-Based Approximation of Interconnect Delay and Slew Modeling in Signoff Timing Tools
Andrew B. Kahng, Seokhyeong Kang,
Hyein Lee
, Siddhartha Nath and Jyoti Wadhwani
VLSI CAD LABORATORY, UC San Diego
15
th
ACM/IEEE System-Level Interconnect Prediction Workshop
June 2
nd
, 2013Slide2
Outline
Motivation
Learning-based Interconnect Modeling
Correlation Methodology with Signoff Timer
Experimental Results
Conclusions and Future WorksSlide3
Motivation
Incremental static timing analysis (
iSTA
)
is the backbone of post-layout design optimization
Using Signoff Timer Using Internal Timer
Gate Sizing/
Vt-Swapping
Post-Layout
Signoff
Post-Layout Optimizer
Iterative invocation
Runtime increase
Timing
Discrepancy
iSTA
Internal Timer
iSTA
Signoff Timer
Runtime increase
Less
accuracy
An accurate internal timer is needed
STA
Signoff TimerSlide4
Motivation
Challenges in matching signoff timer
Error propagation along paths
Error accumulation with
netlist
changes
Error propagation on paths
Error(internal timer – signoff timer)
Error
# logic depth along path
# cell change
Netlist
change
Error accumulation
with
netlist
change
Our goal:
minimize the errorSlide5
Our Work
We minimize divergence ‘d’ between internal and signoff timers
Two basic techniques
Learning-based modeling of wire
delay and slew
Offset-based timing correlation
We achieve small divergence ‘d’
runtimeaccuracy
Signoff
Timer
d
Internal Timer
d
Learning-based modeling
Offset-based timing correlationSlide6
Outline
Motivation
Learning-based Interconnect Modeling
Correlation Methodology with Signoff Timer
Experimental Results
Conclusions and Future WorksSlide7
Preliminary: Delay and Slew
Delay : 50% of input transition to 50% of output transition
Slew : 10
% to 90%
of transition
Gate delay and slew: little divergence between timersLookup table-based method is used not in our scope
Wire delay and slew: challenging to match signoff timerWire delay and slew models in signoff timer are unknown
Delay
Slew
50%
1
0%
9
0%Slide8
Error Distribution
of
Analytical Models
Existing analytical models
Elmore (EM) [Elmore98]
D2M [Alpert00]
PERI [Kashyap02]
Lognormal Slew (
LnS
) [Alpert03]
Wire slew
80%
80%
80%
80%
Regression
EM/
LnS
: overestimate
D2M/PERI: underestimate
Classification
Hard cases cannot be estimated by any single model
Hard cases
Hard cases
Hard cases
Hard cases
Wire delaySlide9
Why Classification?
Data points in each class have stronger linear fit between measured and estimated values after classification
Estimated values
Measured values
Estimated values
Estimated values
Estimated values
Measured values
Measured values
Measured values
Class
2:
Slide10
Classification
Our “alpha” is
chosen empirically
Alpha reflects
degree
of significance of ramp input on delay metric [Kashyap02]
Model 1
Model 2
Model 1
Model 2
Model 3
Wire slew
Wire delay
: wire input slew
m
1
: first moment
m
2
: second moment
Slide11
Learning-based Interconnect ModelingOur methodology
Classification +
Least-Squares R
egression (LSQR)
Collect
training data
LSQR
Classification
Slide12
Learning-based Interconnect ModelingExhaustive search for the best
regressor
(s) and classifier(s
)
Increasing the number of
regressors/classifiers improves the accuracy until a certain point
The number of regressors
The number of classifiers
0
1212
3
20ps23ps
21ps
15%
-8%
-30%
16ps
14ps
-12%
-33%
14ps
0%
Maximum absolute
wire delay error
The number of regressors
The number of classifiers
0
1
2
1
2
373ps
46.8ps46.5ps-36%
-0.0%
-23%
36ps
33ps
-8%
-29%
31.5ps
-4.5%
-11%
32ps
-1.5%
Maximum absolute
wire slew
error
Experimental results with all
testcases
(
ISPD-2013
) Slide13
Learning-based Interconnect ModelingLearning-based models for wire delay and slew
,
,
: regression coefficients for wire delay model
,
: regression coefficients for wire slew model
: wire input slew;
degree of significance of ramp input
: delay metrics for wire;
LNS
: slew metric for wire
Wire delay modeling
Class 1:
-1.72
2.35
0.96
Class 2:
-1.05
1.27
1.02
Class 3:
-2.72
1.41
2.50
Wire delay modeling
-1.72
2.35
0.96
-1.05
1.27
1.02
-2.72
1.41
2.50
Wire
slew
modeling
Class 1:
-3.44
2.07
Class 2:
-2.39
1.59
Class 3:
-1.88
1.30
Wire
slew
modeling
-3.44
2.07
-2.39
1.59
-1.88
1.30Slide14
Outline
Motivation
Learning-based Interconnect Modeling
Correlation Methodology with Signoff Timer
Experimental Results
Conclusions and Future WorksSlide15
Static Timing Analysis
Timing slack is calculated by STA
Endpoint (primary output, input of FF) timing slack errors are reported for evaluation
Calculate
slew
Calculate delay
Calculate AAT/RAT
Calculate slack
3
4
5
6
11
12
15
/15
/12
/11
/6
/5
/6
/5
/2
/0
/0
/0
/0
/0
/2
AAT
/ RAT
/ slack = RAT - AATSlide16
Correlation with Signoff Timer
Use timing information from signoff timer to compensate the difference (error) between internal and signoff timer
Previous work: [Moon10] Endpoint slack offset-based correlation
Can match slack in critical paths
May not be accurate when critical paths change
iSTA
Signoff Timer
iSTA
Internal Timer
Request timing information
offset = signoff timer – internal timerSlide17
Correlation with Signoff Timer
Offset is calculated at each STA stage
Correlated timing (slew/delay/AAT/RAT/slack)
= timing values from internal timer + offset
Calculate slew
Calculate delay
Calculate AAT/RAT
Calculate slack
Slew
Delay
AAT/RAT
Slack
offset = signoff timer – internal timer
Slew offset
Delay
offset
AAT/RAT
offset
Slack
offset
Signoff timer
Internal timerSlide18
Correlation Method vs. Quality
Maximum absolute endpoint slack error for each correlation method
AAT/delay/
AAT+slew
/
delay+slew correlations give 10X more accuracy during netlist changes compared to slack correlation [Moon10]
(ps)
Experimental results with fft testcase (ISPD-2013)
AAT, delay,
AAT+slew, delay+slew correlation
slack correlation
10XSlide19
Timer in Post-Layout Optimizer
Internal timer for a post-layout optimizer
Correlate()
Netlist
change
iSTA
()
# cell change >
N?
Offset
yes
no
invoke signoff timerSlide20
Outline
Motivation
Learning-based Interconnect Modeling
Correlation Methodology with Signoff Timer
Experimental Results
Conclusions and Future WorksSlide21
Experimental Environment
Technology : Liberty from ISPD-2013 Gate Sizing Contest
Testcases
: ISPD-2013
testcasesSignoff tool : PrimeTime© F-2011.06-SP3-7
Benchmark#cells
#nets#PI#FFs#pins#POpci_bridge32
3060330763160335987813
201fft3276633792
10261984
105355
1984matrix_mult
156440
1596423202
2898
4599461600edit_dist
1266651292272562
566137460612Slide22
Error between Internal and Signoff Timer
Maximum absolute endpoint slack error
for
all (delay, slew) pairs
Correlation-based approach can improve
accuracy(delay: D2M, slew: ML) shows the best result
without correlation(ps)
with correlation
Testcase
: fft (ISPD-2013) with correlation
(ps)
(delay: D2M, slew: ML)
10XSlide23
Conclusions and Future
Works
Learning-based
methodology can improve accuracy for
endpoint timing
slack estimationAAT/delay/AAT+slew/delay+slew offset-based correlation methods can achieve 10X
accuracy improvement for timing slack estimationFuture worksEnhance model robustness across different libraries and testcasesMinimize the overhead of correlation methodology with a given accuracyApplication: industry-strength gate sizing optimizersSlide24
Thank
You!