1 2 Two Honda Civics 149Same year same model same colour but are they149Of course not and likewise two chips have 3 Motivation 149PUF Physically Unclonable Function 149Process varia ID: 838025
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1 1 c Design Automation Conference 2 Two H
1 c Design Automation Conference 2 Two Honda Civics
2 •Same year, same model, same colou
•Same year, same model, same colour, but are
3 they•Of course not, and likewise, t
they•Of course not, and likewise, two chips ha
4 ve 3 Motivation •PUF: Physically Un
ve 3 Motivation •PUF: Physically Unclonable Fu
5 nction. •Process variations make fa
nction. •Process variations make fabricated &
6 #149;Use the variations to generate a un
#149;Use the variations to generate a unique –
7 ;Silicon “biometric”; “DN
;Silicon “biometric”; “DNA-like”
8 ;. –Variations uncontrollable
;. –Variations uncontrollable •FPGAs com
9 monly used in embedded systems. 7 PUF A
monly used in embedded systems. 7 PUF Applications
10 •Anti-counterfeiting •IP prot
•Anti-counterfeiting •IP protection
11 9;Cryptography •FPGA-specific appli
9;Cryptography •FPGA-specific applications
12 50;Chip authentication for bitstream loa
50;Chip authentication for bitstream loading 12 Tar
13 get: Xilinx Virtex-5 FPGA SLICESLICEConf
get: Xilinx Virtex-5 FPGA SLICESLICEConfigurable lo
14 gic block (CLB) FFFFFFFFLUTLUTLUTLUT SL
gic block (CLB) FFFFFFFFLUTLUTLUTLUT SLICE SLICE d
15 etails LUTLUTLUTLUT 14 How to Create A S
etails LUTLUTLUTLUT 14 How to Create A Short Pulse?
16 clkclkOUTOUTABLUTs A,B in shiftregister
clkclkOUTOUTABLUTs A,B in shiftregister modeININ c
17 lk 0101…1010……1010…0
lk 0101…1010……1010…0101 0011N1
18 Carry chain multiplexers logic-0logic-1
Carry chain multiplexers logic-0logic-1 N2MUXAMUXB
19 20 Tuning the Pulse Width •Carry ch
20 Tuning the Pulse Width •Carry chains •
20 ;Attained best results A B SLICESLICE P
;Attained best results A B SLICESLICE PREN2 22 Adv
21 antages •PUF completely described i
antages •PUF completely described in HDL –
22 ;Synthesizable. –No matched/manual
;Synthesizable. –No matched/manual routing nee
23 ded. –Easy incorporation into surro
ded. –Easy incorporation into surrounding desi
24 gn •Low area consumption –Two
gn •Low area consumption –Two LUTs, carry
25 chain, and one flip-flop 23 Hardware P
chain, and one flip-flop 23 Hardware Platform 65
26 nm FPGA 24 Experimental Methodology
nm FPGA 24 Experimental Methodology •Six Xilin
27 x Virtex-5 65nm FPGAs. •Implement P
x Virtex-5 65nm FPGAs. •Implement PUF six time
28 s on each •Total: 36 128-bit PUF i
s on each •Total: 36 128-bit PUF implementati
29 ons. –630 pairs of PUFs. •Comp
ons. –630 pairs of PUFs. •Compare “u
30 niqueness”of pairs using 27 PUF Si
niqueness”of pairs using 27 PUF Signature Uni
31 queness 28 Same-Die Signature Uniqueness
queness 28 Same-Die Signature Uniqueness 32 Challen
32 ge/Response … PUF bits ……
ge/Response … PUF bits …… Input chal