Power and Ground Routing 1 Power Planning New technologies Great power budget Dense power grids Reasons Power supply scales more slowly than Moores law Current supplied to chip increase Market demands for functionality ID: 771542
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Power and Ground Routing 1
Power Planning New technologies: Great power budget Dense power grids Reasons:Power supply scales more slowly than Moore’s law Current supplied to chip increaseMarket demands for functionalityUp to 20%-40% of metal resources for P&G nets! 2
Routing Layers Intel’s 45 nm process 3
P&G Bump Top layer metals for clock and Power Lowest resistance 4 Intel’s 45 nm process: Extra-thick ninth Cu metal layer to distribute power to different power-gated domains across the die
Metal Layers 5
Power Planning Power planning: Power routing Placement of power supply IO pads (or bumps) Preferably near highly active regions minimize IR dropPentium 4: uses 223 bumps (out of 423) for P&G 6
P&G Distribution P&G distribution for a custim chip floorplan 7 Trunks connect rings to each other or to top-level power ring Power and ground rings per block or abutted blocks V G G V V V V G G G V V G V V V G G G
Supply Nets Supply nets characteristics: Large Span across the entire chip Routed before any signalUse top two metal layers8
Supply Net Widths Wire widths: Must be adjusted to accommodate their respective estimated branch currents Logic gates: Net segment width: IR drop < 5% VDDWider segments: lower voltage dropSometimes: < 10% VDD (5% for VDD, 5% for Gnd) 9
Types of Power Planning Types: Planar routing Only two supply nets are present A cell needs a connection to both supply netsMesh routingIn most modern chipsCompensates for IR drops 10
11 Planar Routing Step 1: Planarize net topology As both power and ground nets must be routed on one layer Split the design using Hamiltonian path Step 2: Layer assignment Assign net segments to appropriate layers Step 3: Determine widths of net segments A segment’s width ∝ ∑ currents from all the cells to which it connects
Planar Routing Planarize net topology: Hamiltonian path: allows both supply nets to be routed across the with no conflictsGnd enters from left, VDD from right 12 GND VDD © 2011 Springer Verlag
Planar Routing Planarize net topology: Both nets grow in a tree-like fashion Separated by Hamiltonian pathExact routes depend on the pin locations.Cells are connected wherever a pin is encountered. 13
Planar Routing Layer assignment to nets based on: Routability Resistance and capacitance of each available layer Design rule information14
Planar Routing Determine widths of net segments Based on maximum current flow: KCL 15 GND VDD
Planar Routing For large currents Designers extend the “width” of the “planar” route in the vertical dimension with superposed segments on multiple layers that are stapled together with vias.Width determination: iterative process16 current Timing & noise IR drop
17 Mesh Routing Step 1 : Creating a ring Surround the entire core area of the chip, and possibly individual blocks Connects supply I/O cells Electrostatic discharge protection structures May use all layers (except metal1) low resistance Ring Pad Power rail
18 Mesh Routing Step 2: Connecting I/O pads to the ring Each I/O pad: a number of “fingers” Should be maximally connected to the power ring On each of several metal layers low resistance Ring Connector Pad Power rail
19 Mesh Routing Step 3: Creating a mesh A set of stripes at defined pitches on two or more layers Width and pitch: From power consumption And design rules In pairs: Alternating VDD- Gnd , Gnd -VDD Layers: Upper most (thickets) Sparser at lower layers (to avoid signal routing congestion) Ring Mesh Connector Pad Power rail Vias: Stripes on adjacent layers: connected with as many vias as possible
20 Mesh Routing Step 4: Creating Metal1 rails where P&G network meets cells. Width and pitch: Determined by std-cell library Std-cells laid out back-to-back share rails Ring Mesh Connector Pad Power rail VDD GND VDD GND VDD GND VDD GND
21 Mesh Routing Step 5: Connecting the Metal1 rails to the mesh Ring Mesh Connector Pad Power rail
22 Mesh Routing Ring Mesh Connector Pad Power rail © 2011 Springer Verlag M1
23 Mesh Routing 16 16 16 VDD rail GND rail Metal1 Via1 Metal2 Via2 Metal3 Via3 Metal4 VDD Metal4 mesh GND Metal4 mesh M1-to-M4 connection Metal1 rail 1 Metal4 mesh 1 Metal5 mesh 2 Metal6 mesh Metal4 Via4 Metal5 Via5 Metal6 M4-to-M6 connection Metal6 Via6 Metal7 Via7 Metal8 M6-to-M8 connection 4 Metal7 mesh 4 Metal8 mesh © 2011 Springer Verlag M1 M1 to M3: for signal routing M4 to M8: for power routing (2-layers in practice)