Synchronous Demodulator and Configurable Analog Filter Data Sheet ADA FEATURES Demodulates - PDF document

Data Sheet TABLE OF CONTENTSFeaturesApplicationsFunctional Block DiagramGeneral DescriptionRevision HistorySpecificationsSPI Timing CharacteristicsAbsolute Maximum RatingsThermal ResistanceESD CautioPin Configuration and Function DescriptionsTypical Performance CharacteristicsTerminologyTheory of OperationSynchronous Demodulation BasicsADA2200 ArchitectureDecimation FilterIIR FilterMixerClocking OptionsInput and Output AmplifiersApplications InformationAmplitude MeasurementsPhase MeasurementsAmplitude and Phase MeasurementsAnalog Output SystemsInterfacing to ADCsLockIn Amplifier ApplicationInterfacing to MicrocontrollersEEPROM Boot ConfigurationPower DissipationDevice ConfigurationSerial Port OperationData Format Serial Port Pin DescriptionsSerial Port OptionsBooting from EEPROMDevice Configuration Register Map and DescriptionsOutline DimensionsOrdering GuideREVISIONHISTORYRevision Initial Version��Rev. | Page of Data Sheet SPECIFICATIONS3.3CLKINSIHzdefault register configuration, differential input/output, Rto GNDunless otherwise notedTable ParameterTest Conditions/CommentsMinTypMaxUnit SYNCHRONOUS DEMODULATION Measurements are cycle mean values,4 V pp differential, f= 7.8125 kHz Conversion Gain1.01.051.0V/Vrms AverageemperatureDrift/°C Output Offset, Shorted Inputs Average Temperature Drift 6.5  V /°C Power Supply SensitivityChange in output over change in VmV/V Measurement NoiseInput signal at 83°REL Phase Delay (°DELAYInput signal relative to RCLKREL Average Temperature DriftREL/°C Phase Measurement NoiseInput signal at 83°REL9.3RELrms Shorted Input Noise0.1 Hz to 10 Hz CommonMode RejectionkHz to 1kHz offset from fMOD Demodulation Signal BandwidthCLKINMHzkHz INPUT CHARACTERISTICS Input Voltage Range INP or INN to GND0.30.3 CommonMode Input Voltage Range4 V pdifferential input0.2+ 0.2 Singlended Input Voltage Range Reference Input0.2+ 0.2 Signal Input1.0+ 1.0 Input ImpedanceINP to INN Input ignal Bandwidth (3 dB)nput sample and holdcircuitMHz OUTPUT CHARACTERISTICSEach output, R= 10 kto GND Output Voltage Range0.30.3 ShortCircuit CurrentTP or OUTN to GND Common - Mode Output (VOCM) Voltage1.61.651.6 Average Temperature Drift/°C Output Settling Time, to 0.1% of Final Value3.7 V output step, RLOAD= 10 k||10pF,CLKINkHz DEFAULT FILTER CHARACTERISTICSMixing disabled, Vifferential Center Frequency (f7.8125kHz Quality Factor (Q)/(filter 3 dB bandwidth)1.9Hz/ Pass Band Gain= 7.8125 kHz1.05V/V TOTAL HARMONIC DISTORTION(THD)Filter configuration = LPFat NYQ850 Hz4 V pp differentialinput Second Through Fifth Harmonics  80 dBc CLOCKING CHARACTERISTICS CLKIN Frequency Range ( f CLKIN ) T A =  40°C to +85°C CLKIN [2:0] = 2562.56MHz CLKIN [2:0] = 640.64MHz CLKIN [2:0] = 160.16MHz CLKIN [2:0] = 10.01MHz MaximumCLKIN FrequencyWhile booting from EEPROM12.8MHz ��Rev. | Page of Data Sheet ParameterTest Conditions/CommentsMinTypMaxUnit DIGITAL I/O Logic ThresholdsAll inputs/outputs Input Voltage Low0.8 High 2.0 V Output Voltage LowWhile sinking 200 HighWhile sourcing 200 Maximum Output CurrentSink or source Input Leakage Internal PullUp Resistance BOOT and RST only 40 k CRYSTAL OSCILLATOR Internal Feedback Resistor LKIN Capacitance XOUT Capacitance POWER REQUIREMENTS Power Supply Voltage Range3.6 Total Supply Current Consumptio See the Terminologysection.Commonmode signal swept from fMOD1 kHz to fMOD+ 1 kHz. Output measured at frequency offset from fMOD. For example, a commonmode signal at fMODHz is measured at 500 Hz.The input impedance is equal to a 4 pF capacitor switched CLKIN. Therefore, the input impedance = 10/(2fCLKIN× 4).SPI IMINGCHARACTERISTICS2.7 to 3.6default register configuration40 to +8, unless otherwise notedTable . SPI TimingParameterTest Conditions/CommentsMinTypMaxUnit SCLK50% ± 5% duty cycleMHz t CS CS to SCLK edge SCLK low pulse width SCLK high pulse width DAVData output valid after SCLK edge DSUData input setup time before SCLK edge DHDData input hold time after SCLK edge Data output fall time t DR Data output rise time 1 ns SCLK rise time SCLK fall time DOCSData output valid after CS edge SFS CS high after SCLK edge ��Rev. | Page of Data Sheet Figure . SPI ead iming iagram(SPI aster ead from the ADA2200Figure . SPI rite iming iagram(SPI aster rite totheADA2200Table EEPROM MasterC Boot TimingParameteSymbolMinTypicalMaxUnit BOOT Load from BOOT Complete9600CLKIN cycles RST to BOOT Setup Time CLKIN cycles BOOT Pulse WidthCLKIN cycles RESET Minimum RST ulse idth START CONDITION BOOT Low Transition to Start ConditionCLKIN cycles CLKIN cycles with CLKIN DIV[2:0]set to 000. SCLKSDO(MISO)DATA BITSLSBSDIO(MOSI)MSB INDATA BITSLSB IN tSL tCS tSH SFS tSF tSR tDRtDF tDAV DSU 12295-003 SCLKSDIO(MOSI)MSB INDATA BITSLSB IN tSL tCS tSH SFS tSF tSR DSU 12295-004 ��Rev. | Page of Data Sheet Figure . Load from EEPROM iming iagramFigure CLKIN to RCLK, SYNCOand OUTP/OUTample imingTable . Output, SYNCO, and RCLK Timingefault egister ettingsParameterTest ConditionsCommentsMinTypMaxUnit CLKIN to OUTsample update delay CLKIN to SYNCO delay, risingor fallingedgeto risingedge SYNCO pulse width1/f CLKIN to RCLK delay, rising edge to rising or falling edge Figure . Input, Output, SYNCOand RCLK Timing elative to CLKIN RSTBOOTSCLSDASTARTb10001R/WDATASTOPREGISTER ADDR[1:0] 12295-005 SAMPLE 0SAMPLE 1SAMPLE 2SAMPLE 3 + 4 HOLD SAMPLESOUTPUTPHASE90 = 1CLKINRCLKSYNCO12295-006 HOLD SAMPLES SAMPLE 0SAMPLE 1SAMPLE 2SAMPLE 3 + 4 HOLD SAMPLESSAMPLE 0SAMPLE 1 OUTPUTPHASE90 = 0 CLKINRCLKSYNCOINx, OUTxINN/INPOUTN/OUTP t1t2t3t4 12295-007 ��Rev. | Page of Data Sheet ABSOLUTE MAXIMUM RATINGSTable ParameterRating Supply Voltage Output ShortCircuit CurrentDurationIndefinite Maximum Voltage at ny nput+ 0. Minimum Voltage at ny npuGND OperationalTemperature Range40°C to + Storage Temperature Range65°C to +150 Package Glass Transition Temperature ESD Ratings Human Body Model (HBM)1000 Device Model (FICDM) Machine Model (MM) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliabilityHERMALESISTANCEis specified for a device in a natural convection environment, soldered on layer JEDEC printed circuit board (PCB).Table PackageUnit Lead TSSOP14.8C/W ESD CAUTION ��Rev. | Page of Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIFigure Pin ConfigurationTable . Pin Function Descriptions Pin No. Mnemonic Description CLKINSystemlock nput SYNCOSynchronization ignal utput 3 CS /A0Serial nterface hip elect nput/Boot EEPROM ddress 0 nput 4 BOOT Boot from EEPROM ontrol nput GNDPower upply round INPNoninverting ignal nput INNInverting ignal nput VOCMommonode oltageutput 9 RST Reset ontrol nput OUTNInverting utput OUTPNoninverting utput VDDPositive upply nput SDOReference Clock Output/Serial nterface ata utputin 4ire SPI ode SDIBidirectional erial ata (nput nly iire SPI ode)/Iidirectional ata K/SCLSerial nterface lock nput/Ilockutput XOUTCrystal river utput. Place a crystal between this pinand CLKINor leave this pin disconnected 12345678 SYNCOCS/A0BOOTINNINPGNDCLKINSCLK/SCLSDIO/SDARCLK/SDOOUTNVOCMRSTOUTPVDDXOUTADA2200TOP VIEW(Not to Scale) 12295-008 ��Rev. | Page of Data Sheet TERMINOLOGYCycle MeanThe cycle mean is the average of all the output samples (OUTP/OUTN) over one RCLK period. In the default configuration, there are eight output samples per RCLK cyclethus,the cycle mean is the average of eight consecutive output samples. If the device is reconfigured such that the frequency of RCLK is f/4, then the cycle mean is the average of four consecutive output samples.Conversion GainConversion ain is calculated as follows: GainConversion whe牥is the offset corrected cycle mean, PHASEbit = is the offset corrected cycle mean, PHASEbit = is the rms value of the input voltage.The offset corrected cycle mean = cycle mean  output offset. Relative Phase ( 剅L Relative phase is the phase difference between the rising positive zero crossing of a sine wave at the INN/INP inputs relative to the next rising edge of RCLK.Figure 14. Example Showing Relative Phase, RELof 37 Phase Delay DEL䅙 The phase delay is the relative phase (REL) that produces a zero cycle mean output value for a sine wave input with a frequency equal to fRCLK. The phase delay is the relative phase value that corresponds to the positive zero crossing of the phase measurement transfer function.Phase Measurement Transfer FunctionFigure shows the cycle mean value of the output for a rms input sine wave as RELis swept from 0° to 360Figure 15Phase Transfer Functionwith Phase Delay of 83°, 1 V rmsInput RCLK INP/INNPHASE (Degrees) RELATIVEPHASE = 37° 12295-009 1.2–1.2–1.0–0.8–0.6–0.4–0.20.20.40.60.81.0CYCLE MEAN VALUERELATIVE PHASE (REL12295-010 ��Rev. | Page of Data Sheet THEORY OF OPERATIONThe ADA2200is a synchronous demodulatorand tunable filterimplemented withampledanalog technology (SAT).Synchronous demodulators, also known as ockin mplifiers, enable accurate measurement osmall acsignals in the presence of noise interference orders of magnitude greaterthan the signal amplitude. Synchronous demodulators use phasesensitive detection to isolate the component of the signal at a specific reference frequency and phase. Noiseat frequencies that are offset from the reference frequencyare easily rejected and do not significantly impair the measurement.works on the principle of charge sharing. A sampled analogsignal is a stepwise continuous signal without amplitude quantization. This contrasts with a signal sampled by an ADC, which becomes a discrete time signal with quantizedamplitude. With SAT, the input signalis sampled by holding the voltageon a capacitor at the sampling instant.Basic signal processing can then bperformedin the analog domain by charge sharing amongcapacitors. The ADA2200includes an analog domain lowpass decimation filter, programmable IIR filterand a mixer.This combination offeatures enables reduced ADC sample rates and lowers the downstream digital signal processing requirements if the signal digitized. The output of the ADA2200can also be used in an all analog signal path. In these applications,add a reconstruction filter following the ADA2200in the signal path.SYNCHRONOUS DEMODULATION BASICSEmploying synchronous demodulation as a sensor signaling conditioning technique can result in improved sensitivity when compared to other methodsSynchronous demodulation adds two keybenefitsforrecovering small sensor output signals in the presence of noiseThe first benefit being the addition of an excitation signal, whichenablesthe sensor output signal to be moved to lower noise frequency band.The second benefit is that synchronousdemodulation enablesa simple lowpassfilter to remove most of the remaining undesired noise components.Figure shows a basic synchronous demodulation systemusedfor measuring the output of a sensor.Figure 16. Basic ynchronous emodulator lock iagramA carrier signalMODexcitethe sensor. This shifts the signal generatedby the physical parameter being measured by the sensor to the carrier frequency.This shift allows the desired signal o be placed in a frequency band with lower noiseimproving the accuracyof the measurement. A bandpass filter (BPF)removesome of the outband noise. A synchronous demodulator(or mixer) shifts the signal frequency back to dc. The last stagelowpass filter removemuch of the remaining noise. Figure and Figure show the frequency spectrum of e signal at different points in the synchronous demodulator.Figure 17. Output pectrum of ynchronous emodulator efore emodulationFigure 18. Output pectrum of ynchronous emodulator fter emodulationPhase Sensitive DetectionSynchronous demodulation uses the principle of phase sensitive detection to separate the signal of interest from unwanted signals.In Figure , themixer performsthe phase sensitive detectionThe signal at the mixer output (C) is the product of the referencesignal and a filtered version of the sensor output(B). f the reference signal is a sinewave, the physical parameter is aconstant and there is no noise in the systemhe signal at the output of the BPF a sinewave that can be expressed as sin(REF LPF SENSOR PHYSICALPARAMETERNOISEMOD D REFBPF 12295-017 REF NOISE AT A SENSORSIGNAL AT A, B NOISE AT BPHYSICALPARAMETER 12295-018 REF NOISE AT DNOISE AT CSENSORSIGNAL AT C, D 12295-019 ��Rev. | Page of Data Sheet The output of the mixer (if implemented as a multiplier) is thenREFcos(REFREFcos(2REFREFThis signal is a dc signal and an ac signal at twice the reference frequency. If the LPF is sufficient to remove the ac signal, the ignal at the LPF output (D) is REFcos(REFThe LPF outputis a dc signal that is proportional to both the magnitude and phase of the signal at the BPF output (B). When the input amplitude is held constant, the LPF outputenables be used to measure the phase.When the input phase is held constant, the LPF canbe used to measure amplitude.Note that the reference signal is not required to be a pure sinewave. The excitation signal and demodulation signal must only share a common frequency and phase to employ phase sensitive detection.In some applicationsit may be possible to use the squarewave output from the ADA2200RCLK output directly.Internal to the ADA2200the demodulation is performed not by multiplying the REFCLK signal with the input signal, but by holding the output constant for ½ the sample output periods.This operation is similar to a half wave demodulation of the input signal.For more information on signal detection using this function, seethe pplicationsInformationsectionADA2200ARCHITECTUREThe signal path fortheADA2200consists of ahigh impedance inputbuffer followed by a fixed lowpass filter (FIR decimation filter, programmableIIR filter, a mixerfunctionand a differential pin driver. Figure shows adetailed block diagram of the ADA2200. The signal processing blocks are all implemented using a charge sharing technique.Figure 19ADA2200ArchitectureDECIMATION FILTERThe clock signal divider (after CLKIN) determines the input sampling frequency,SIof the decimationfilter. The decimation filterproduces one filtered sample for every eightinput samples. Figure shows thewideband frequency response of the decimationfilterBecause the filter operates onsampled data, images of the filter appearat multiples of the input sample rate. The stopand of the decimation filter begins around ½ of the output data rateBecausean image passband exists around SIny undesired signals in the passband arounSIalias to dc and areindistinguishable from the low frequency input signal.To preserve the full dynamic range of the ADA2200use inputantialiasing filterif noise at frequencies bove7.5is not lower than the noise floor of the frequencies of interest.firsorder lowpass filter is usually sufficient for the antialiasing filter.Figure 20Decimation ilter requency esponse Figure shows a more narrowbandwidth view of the decimation transfer functionThe stop band of the decimation filter starts at ½ of the output sample rateThe stopband rejectionof the decimatorlowpass filter is approximatelydB.The passband of the decimation filter extends to 1/4of the output sample rateor 1/32of the decimator input sample rate.Figure 21Decimation ilter ransfer unction, f= 800 INP INN OUTP OUTN VOCM SCLK/SCL SDIO/SDA CS/A0 RCLK/SDO VDD LPF 8 PROGRAMFILTER CLOCKGEN CONTROLREGISTERS BOOT FROMEEPROM (I VCM n+1 ÷2m ÷8 90° MODXOUT CLKIN SYNCO GND RST BOOT ADA2200 12295-020 0.5 fSO 2fSO 7.5f 8fSO =fSIfSI –ffSI +f 8.5f 12295-021 GAIN (dB)FREQUENCY 12295-022 ��Rev. | Page of Data Sheet IIR FILTERThe IIR block operates the output sample rate, f, which is at 1/8of the input sample rateSIBy default, the IIR filter is configured as abandpass filterwith a center frequency at fSI/64)This frequency corresponds to thedefault mixing frequency and assures that input signals in the center of the passband mix down to dc.Figure shows the default frequency response of the IIR filter.Figure 22. Default IIR ilter requency esponse/8 BPF)If a different frequency response is required, the IIR can be programmed fora different response. Register11 through Register 27 contain coefficient values that program the filter response. To program the filter, first loadtheconfigurationregisters (Register 11 through Register with the desired coefficients. The coefficients can then be loaded into the filter by writing 0x03 to egister 0xThe IIR filter can be configured for allpass operation by loading the coefficients listed in Table able . IIR Coefficients for the All ass ilterRegisterValue 0x00110xC0 0x00120x0F 0x00130x1D 0x00140xD7 0x00150xC0 0x00160x0F 0x00170xC0 0x00180x0F 0x00190x1D 0x001A0x97 0x001B0x7E 0x001C0x88 0x001D0xC0 0x001E0x0F 0x001F0xC0 0x0020 0x0F 0x00210xC0 0x00220x0F 0x00230x00 0x00240x0E 0x0025 0x23 0x00260x02 0x00270x24 MIXERThe ADA2200performs the mixing function by holding theoutput samplesconstant for ½ of the RCLKperiod.his is similar to a halfwave rectification function except that the output does not return to zero for ½ the output period, but retains the value of the previous sample.In the default configuration, thereare eightoutput sampleperiods during each RCLK cycle. There are fourupdated output sampleswhile the RCLK signal is high. While RCLK is low, the fourthupdated sample held constant for fouradditional output sample periods. The timing of the output samples in the default configuration is shown in Table The RCLK divider, RCLK DIV[1:0], can be set to divide by 4. When this mode is selected, four output sample periods occur during each RCLK cycle. Two output samplesoccur while the RCLK signal is high. While RCLK is low, the second updated sample is held constant for two additional output sample periods. The mixer can be bypassed. When the mixer is bypassed, the outputproducean updated sample value every output sample period. GAIN (dB)NORMALIZED FREQUENCY (Hz/Nyquist)0.500.751.000.25 12295-023 ��Rev. | Page of Data Sheet PhaseShifterIt is possible to change the timing of the output samples with respect to RCLK by writing to the PHASE90 bit in egister 2A. When the alternative timing option is selected, two output samples are updated while RCLK is low, and two are updated while RCLK is high.The second sample, which istaken while RCLK is highis held fouradditional output sample periods. The timing is shown in Figure Applying a 90phase shift can be useful in a number of instances.It enables a pair of ADA2200devices to perform inphase and quadrature demodulation. A 90phase shift can also be useful in control systems for selecting an appropriate error signal output.Figure 23. Output Sample Timing Relative to RCLK, (A) HASE90 , (B) HASE90 CLOCKING OPTIONSThe ADA2200has several clocking options to make system integration easier. Clock DividersThe ADA2200has a pair of onchip clock dividers generatethe system clocksThe input clock divider, CLKIN DIV[2:0], setsthe input sample rate of the decimatorby dividing the CLKINsignal. The value of CLKIN DIVV2:0can be set to1, 16, 64or 256. The output sample rate (f) is always 1/8of the decimator input sample rate. The RCLK divider, RCLK DIVV1:0, sets the frequency of the mixer frequency, f(which is also the frequency of RCLK) by dividing by either 4 or 8.Synchronization Pulse OutputThe ADA2200generates an output pulse(SYNCO)which can be used by a microprocessor or directly byan ADCto initiate an analog to digital conversion of the ADA2200output.SYNCO signalensurethat the ADC sampling occurs at an optimal time during the ADA2200output sample window.ne output sample of the ADA2200is 8 fclock cycles long.The SYNCO pulse is clock cycle in duration.As shown in Figure , the SYNCO pulse can be programmed to occur atof 16 different timing offsetsThe timing offsets arespaced at ½ clock cycle intervalsand span the full output samplewindow.The SYNCO pulse can be inverted, or the SYNCO output can be disabled. Theoperation of the SYNCO timing generation configuration settings are contained in egister 0xFigure 24. SYNCO utput imingelative to OUTP/OUTN, INP/INand CLKIN (A)(B)12295-024 INx, OUTx SYNCO (0) SYNCO (1) SYNCO (13) SYNCO (14) SYNCO (15) CLKIN 12 12295-025 ��Rev. | Page of Data Sheet INPUT AND OUTPUT AMPLIFIERSSinglended onfigurationsIf a singleended input configuration is desired, the input signal musthave a commonmode voltage near midsupply.Decouplehe other inputs to the commonmode voltage of the input signal.Note that differences between the commonmode levels between the INP and INN inputs result in an offset voltage inside the device.Even though the BPF removethe offset, minimize the offset to avoid reducing the available signal swing internal to the device.For singleended outputs, either OUTP or OUTN can be used. ave the unused output floating.Differential ConfigurationsUsing the ADA2200in differential mode utilizethe full dynamic range of the device and providethe best noise performance and commonmode rejection.��Rev. | Page of Data Sheet PPLICATIONSINFORMATIONThe signal present at the output of the ADA2200depends on the amplitude and relative phase of the signal applied at it inputs.When the amplitude or phase is known and constant, any output variations can be attributed to the modulated parameter.ereforewhen the relative phase of the input is constant, the ADA2200performs amplitude demodulation. When the amplitudeis constant, the ADA2200performs phase demodulation.The sampling and demodulation processes introduce additional frequency components onto the output signalIf the output signal of the ADA2200used in the analog domain or if it sampled asynchronously to the ADA2200sample clock, thesehigh frequency components can be removed by following the ADA2200with a reconstruction filter. If the ADA2200output sampled synchronously to the ADA2200output sample rate, an analog reconstruction filter is not required becausethe ADC inherently rejectsampling artifacts.The frequency artifacts introduced by the demodulation process can be removed by digital filtering. MPLITUDE MEASUREMENTIf the relative phase of the input signal tothe ADA2200remains constant, the output amplitude directly proportional to the amplitude of the input signal. Notethat the signal gain is unction ofthe relative phase of the input signal. Figure shows relationship between the cycle mean outputand the relative phasehe cycle mean output voltage isCYCLEMEANConversion ainIN(RMS)× sin(RELDEL1.05 IN(RMS)× sin(RELDELThereforethe highest gainandthus thelargest signalnoise ratio measurement, is obtained when operating the ADA2200with RELDEL+ 90° = 173°. This value of RELis also the operating point with the lowest sensitivity to changes in the relative phase. Operating with RELDELoffers the same gain and measurement accuracy, but with a sign inversion.PHASE MEASUREMENTSIf the amplitude of the input signal to the ADA2200remains constant, the output amplitude a function of the relative phase of the input signalThe relative phase can be measured asREL= sinCYCLEMEANConversionainIN(RMS))) + DELsinCYCLEMEAN/(1.05 × IN(RMS)DELNote that the output voltage scales directly with the input signal amplitude. A fullscale input signal provides the greatest phase sensitivity (V/°RELand thus thelargest signalnoise ratio measurement. The phase sensitivity also varies with relative phase. The sensitivity is at a maximum when REL= 83. For this reason, the optimal measurement range is for input signals with a relative phase equal to the phase delay. This rangeprovidethe highest gain and thus thelargest signalnoise ratio measurement.Thisrangeis also the operating point with the lowest sensitivity to changes in the relative phase. Operating at a relative phaseequal to the phase delayof to offers the same gain and measurement accuracy, but with a sign inversion. The phase sensitivity with a p differentialinputoperating with a relativephase that is equal to the phase delayresults in a phase sensitivity of 36.6mV/RELAMPLITUDE AND PHASE MEASUREMENTSWhen both the amplitude and relative phase of the input signals are unknown, it is necessary to obtain two orthogonal components of the signal to determine its amplitude, relative phase, or both. These two signal components are referred to as the inphase (I) and quadrature (Q) components of the signal.A signal with two known rectangular components is representedas a vector or phasor with an associated amplitude and phase(see Figure Figure 25. Rectangular and olar epresentation of a ignalIf the signal amplitude remainnearly constant for the duration of the measurement, it is possible to measureboth the I and the Q components of the signal by toggling the PHASE90 bit between two consecutive measurements.To measurethe I component, set the PHASE90 bit to 0. To measure the Q component, set the PHASE90 bit to 1.Afterboth the I and Q components have been obtained, it is possible to separate the effects of the amplitude and phase variations. Then, calculate themagnitudeand relative phase using the following formulas: 22QIA cos Or alternatively sin QAIIIIIVIII 12295-026 ��Rev. | Page of Data Sheet The inverse sine or inverse cosine functions linearize the relationship between the relative phase of the signal and the measured angle. Becausethe inverse sine and inverse cosine are only defined in two quadrants, thesign of I and Q must be considered to map the result over the entire 360range of possible relative phase values. The use of the inverse tangent function is not recommended because the phase measurements become extremely sensitive to noise as the calculated phase approaches ANALOG OUTPUT SYSTEMWhen the output signal of the ADA2200is used in the analog domain or if it issampled asynchronously to the ADA2200sample clock, it is likely that a reconstruction filter required. Reconstruction FiltersThe bandwidth of the analog reconstruction filter sets the demodulation bandwidth of the analogoutput.There is a direct tradeoff between the noise and demodulation bandwidth. Therefore, it is recommended to ensure that the reconstruction filter cutoff frequency as low as possible while minimizing the attenuation of the demodulated signal of interest.Similar to a digitalanalog converter (DAC, the output of the ADA2200is a stepwise continuous output. This waveform contains positive and negative images of the desired signal at ltiples ofSO. In most cases, the images are undesired noise components that must be attenuated. The lowest frequenimage to appear in the output spectrum appearat a frequency ofhe image amplitude reduced by the sin(x)/x rolloff. System accuracy requirements may dictate that additional lowpass filtering is required to remove the output sample images.INTERFACING TO ADCSSettling Time ConsiderationsIf the ADC coherently sampling the ADA2200outputs, design the output filter to ensure that the output samples settle prior to ADC sampling.The output filter does not need to remove the sampling images generated by the ADA2200The images areinherently rejected by the ADC sampling process.Clock SynchronizationThe SYNCO output can trigger the ADC sampling processdirectly, or a microcontroller can use SYNCO to adjust the ADC sampling time.Adjusting the SYNCO pulse timing can maximize the available time for the ADA2200outputs to settle prior to ADC sampling.Multichannel ADCsIn multichannel systems that require simultaneous sampling, the ADA2200can provide per channel programmable filtering and simultaneous sampling.Figure shows an channel system with a 1MHz aggregate throughput rate. The ADA2200samples each channel at 1 MSPS nd produces filtered samples at an output sample rate of 125 kHz each. The AD7091Ris an channel, 1MHz ADC with multiplexed inputswhich cyclethrough the eightchannels at kHz, producing an aggregate output sample rate of 1MHz.Figure 26ADA2200in an 8hannel imultaneous ampling pplicationLOCKIN AMPLIFIER APPLICATIONFigure shows the ADA2200in a lockin amplifier application.The 80 kHz master clock signal sets the input sample rate of the decimation filter, fSIThe output sample rate kHz. In the default configuration, the excitation signal generated by RCLK 1.25kHz.This is also the center frequency of the onchip IIR filter. In many cases, the RCLK signal buffered to provide a squarewaveexcitation signal to the sensor.It may also be desirable to provide further signal conditioning to provide a sinewave excitation signal to the sensor.A low noise instrumentation amplifier providesufficient gain to amplify the signal so that the noisefloor of the signal into the ADA2200is above the combined noise floor of the ADA2200and the ADC referred to the ADA2200inputs.Figure 27. Lockmplifier pplicationIn default mode, the ADA2200produces eightoutput samples for every cycle of the excitation (RCLK) signal.There are fourunique output sample values. The fourth value appearon the output for fiveconsecutive output ample periods. SIMULTANEOUSSAMPLING ANDFILTERING8 CHANNELSSIMULTANEOUSLYSAMPLEDAT 125kHz EACHMICRO-CONTROLLER CH1CH2 ADA2200SYNCO ADA2200 ADA2200 12-BIT 8:1MUX SEQUENCER AD7091R-8 IRQCLK0 SCLKSCLK DOUTMISO DINMOSI CLKIN 1MHzSAMPLECLOCK12295-028 12295-029 CLKIN SYNCO RCLK/SDO INP OUTP INN OUTN VOCM VDD GND ADA2200 SENSOREXCITATIONCONDITIONING3.3V SENSORREFAD8227 AD7170 MASTERCLOCK AD8613 ��Rev. | Page of Data Sheet There are several ways of digitally processing the output samples to optimize measurement accuracy, bandwidthand throughput rate. One method to take the sum of eightsamples to return a value.A moving average filter lowerthe noise floor of the returned values.The length of the moving average filter determined by the noise floor and settling time requirements.INTERFACING TO MICROCONTROLLERSThe diagram in Figure shows basic circuit configuration driven by a lowpower microcontroll(the ADuCM361. In this case, the ADA2200reduces the ADC sampling rate by a factor of 8, and reduces the subsequent signal processing required by the microcontroller.Figure 28Fullyrogrammable onfigurationInterface to ower icrocontrollerEEPROM BCONFIGURATIONThe diagram in Figure shows a standalone configuration withEEPROM boot fortheADA2200. The standard oscillator circuit between CLKIN and XOUT generates the clock signal. Holding BOOT low duringpoweron reset(POR)forcesthe ADA2200to load its configuration from a preprogrammed EEPROM. An EEPROM boot is alsoinitiated by bringing the BOOT pin low while the device in not in reset.Figure 29StandaloneonfigurationPOWER DISSIPATIONThe ADA2200current draw is composed oftwo maicomponents, the amplifier bias currents and the switched capacitor currents. The amplifier currents are independent of clock frequencythe switched capacitor currents scale in direct proportion toSIFigure shows the ADA2200measured typical current draw at supply voltages of 2.7and 3.3V, as the input clock varies from Hz to 1MHzwith CLKIN DIV[2:0] . With a3.3V supply voltage, the current draw can be estimated with the following equation:CLKINhere CLKINis specified in kHz.Figure 30Typical Current raw vsCLKIN Frequency2.7 and 3.3 INP OUTP OUTN CLKIN SYNCO RST BOOT CS/A0 SDIO/SDA RCLK/SDO SCLK/SCLAIN0AIN1P1.2P0.6/IRQ2P1.1P1.0P1.7/CS0P1.6/MOSI0P1.4/MISO0P1.5/SCLK0 P0.3/CS1 AVDD_REG DVDD_REG AGND VREF– IOVDD AVDD VREF+ P0.0/MISO1 P0.2/MOSI1 P0.1/SCLK1 VOCM XOUT GND VDD ADA22003.3V INN TO HOST,MEMORYINTERFACE0.47µF0.47µF ADuCM361 12295-030 NOTES1. SOME PIN NAMES OF THE ADuCM361 HAVE BEEN SIMPLIFIED FOR CLARITY. VDD ADA22003.3V SCL A0 SDA SCLK/SCL SDIO/SDA CS/A0 A1 A2 EEPROM*T24C02 OR EQUIALENT 3.3V RCLK/SDO OUTN OUTP VOCM INN RST BOOT CLKIN XOUT INP OUTPUT EXCITATION INPUT GND3.3V12295-031 (µA)CLKIN FREQUENCY (kHz) 2.7V3.3V12295-032 ��Rev. | Page of Data Sheet DEVICE CONFIGURATIONThe ADA2200has several registerthatcan be programmed to customize the device operation.There are two methods for programming the registershe device can be programmed over the serial port interfaceor the IC master can be used to read the configuration from a serial EEPROM.SERIAL PORT OPERATIONThe serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industrystandard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the ADA2200Singlebyte or multiplebyte transfers are supported, as well aMSB first or LSB first transfer formats. The serial port interface can be configured as a singlepin I/O (SDIO) or as two unidirectional pins for input and output (SDIO and SDO).A communication cycle with the ADA2200has two phases. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cyclePhase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, along withthe starting register address for the first byte of the data transfer. The first SCLK rising edges of each communication cycle are used to write the instruction byte into the device.A logic high on the CS /A0pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next rising SCLK edges represent the instruction bits of the current I/O operation.The remaining SCLK edges are for Phase 2 of the communicationcycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediatelyupon writing to the last bit of each transfer byteDATA FORMATThe instruction byte contains the information shown in Table 9Table . Serial Port Instruction ByteLSBI15 R/ W A14 A13 A12 …A2 A1 A0 R/ W , Bit 15of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logicindicates a read operation, and Logic 0 indicates a write operation.A14 to A0, Bit 14to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers,A14is the startingyte address. The remaining register addresses are generated by the device based on the LSB firstbit (Register0x00, Bit 6).SERIAL PORT PIN DESCRIPTIONSSerial Clock (SCLK/SCLThe serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input is registered on the rising edgeof the SCLKsignal.All data is driven out on the falling edge of he SCLKsignalChip Select ( CS /A0An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. When the CS /A0pin is high, the SDO and DIO signals go to a high impedance state. Keep the CS /A0pin low throughout the entire communication cycle. Serial Data I/O (SDIO/SDAData is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit3 and Bit . The default is Logic0, configuring the SDIO/SDApin as unidirectional.Serial Data OutpuRCLK/SDO)If the ADA2200is configured for 4wire SPI operation, this pin can be used as the serial data output pin. If the device is configuredfor 3wire SPI operationthispin can be used as an output for the reference clock (RCLK) signal. Setting the RCLK elect bit egister 0x2A, it 3) high activates the RCLK signal. SERIAL PORT OPTIONSThe serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB firstbit (Register00, Bit 6). The default is MSB first (LSB first= 0).WhentheLSB firstbit = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequentdata bytes follow from high address to low address. In MSB first mode, the serial port internal byte address generator decrementsfor each data byte of the multibyte communication cycle.When the LSB firstbit , the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB first format startwith an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes follow from the low address thehigh address. In LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle.If the MSB first mode is active, the data address is decremented for each successive read or write operation performed in a multibyte register access. If the LSB first mode is active, the data address increments for each successive read or write operation performed in a multibyte register access��Rev. | Page of Data Sheet Figure 31. Serial Port Interface Timing, MSB FirstFigure 32. Serial Port Interface Timing, LSB FirstBOOTINGFROM EEPROMThe device can load the internal registers from the EEPROM using the internal IC master to customize the operation of the ADA2200To enable this feature, the user must control either the RST pin or the BOOT pin.In either case, the deviceboots from the EEPROM only when it is out of reset and the master clock is active. Enabling Load rom MemoryA boot from the EEPROM is initiated by two methods. To initiate loading via the BOOT pin, the devicemust be out of resetand the BOOT pin is broughtlow for a minimum of two clock cycles of the master clock. After it isinitiated, the boot completeirrespective of the state of the BOOT pin. To initiate subsequent boots, the BOOT pin must be brought high and then low for a minimum of two clock cycles of the master clock. To initiate loading via th RST pin, the BOOT pin must be low. The RST pin can be tied high and the ADA2200loadfrom the EEPROM when the deviceis poweredup and the internal POR cycle completes. To initiate subsequent boots, the ADA2200can be power cycled or the RST pin can be brought low and then high.The SPI interface is disabled while the ADA2200is loading the EEPROM.Load from Memory CycleThe ADA2200reads the first bytes of the EEPROM. The first 27 bytes represent the contents to be loaded into Register 0x11 to Register 0xByte 28contains the checksum stored in the EEPROM. The ADA2200calculates the checksum for the first bytesthatit reads back and compares it to the checksum in the EEPROM. The ADA2200calculated checksum is accessible by reading the EEPROM checksum register (Register 0xE). If the ADA2200checksum matches the checksum stored in the EEPROM, the load from the EEPROM was successful. The load from the EEPROM pass or fail status is recorded in the EEPROM staturegister (Register 0xF).In addition, the LSB of the EEPROM status register indicates whether the load cycle is complete. Logic 1 represents successfulcompletion of the load cycle. Logic0 represents the occurrenceof timeout violation during the loading cycle. In the eventof a timeout or the successful completion of the load from a memorycycle, the ADA2200C master interface disables, and the ADA2200SPIinterface reenables, allowing the user communication accessto the deviceThe load cycle completewithin 10000 clock cycles of CLKIN (or CLKIN divided by the current value of CLKIN DIVV2:0] if the load cycle is being initiated by the BOO pinDual Configuration/Dual Device Memory LoadThe CS /A0 pin allows a single EEPROM device to support a dual configuration for a single ADA2200device or different configurations for two different ADA2200devices.To ensure reliable operation,setthe CS A0 pin to the desired state beforeinitiating a bootand then hold the state for the entire duration of the boot.To configure a single ADA2200device, the EEPROM must have a word page size that supports a minimum of 32 words, each ofbits per word. To support twodevices, or a dual configuration for a single device, the EEPROM must have at least twoword pages.TheADA2200configuration data for each device must be allocated to the EEPROMmemory withina single word page.Using SPI Master with EEPROM LoadingThe load from a memory cycle requires an IC communication bus between the ADA2200and the EEPROM device; however, the ADA2200can still be controlled by the SPI interface after the load from the memory cycle is complete. It is recommendedthat the CS A0 pin return to logic high after the load from the memory cycle and before the first SPI read or write command. This allows the user to ensure that the proper setup time elapses before the initiation of a SPI read/write command (see Table R/WA14A13INSTRUCTIONCYCLEDATATRANSFERCYCLESCLKSDIO CS 12295-033 A12A13A14INSTRUCTIONCYCLEDATATRANSFERCYCLESCLKSDIO CS R/W 12295-034 ��Rev. | Page of Data Sheet DEVICE CONFIGURATIONREGISTER MAP AND DESCRIPTIONSTable . Device Configuration Register MapAddr(Hex)Register NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Default 0x0000Serial nterfaceResetLSB firstAddress incrementSDO ctiveSDO active Address incrementLSB firstReset0x00 0x0006Chip Die evision[3:00x00ead only) 0x0010 Filter s trobe 0 0 0 0 0 0 Load coefficients[1:0] 0x00 0x 00 11 to 0x0027 Filter onfigurationCoefficient[7:0]Table 0x0028Analog pin configurationINP gainClock source select0x00 0x0029Sync controlSYNCO output enableSYNCO invertSYNCO dge selectt3:00x2D 0x002ADemod controlHASEMixer enableRCLK selectVOCM electct2:00x18 0x002BClock configurationCLKIN DIVV2:0RCLK DIVV1:00x02 0x002CDigital pin configurationRCLK/SDOoutput enable0x01 0x002DCore resetCore reset0x00 0x002EChecksumChecksum value[7:0]N/A (read only) 0x002FEEPROM tatusChecksum failedChecksum passedBoot from EEPROM completeN/A (read only) X means don’t care. N/A means not applicable.Table DeviceConfigurationRegisterDescriptionsNameAddress (Hex)BitBit NameDescriptionDefault Serial nterface0x00ResetWriting a 1 to this bit places the device in reset. The device remainsin reset until a 0 is written to this bitAll of the configuration registers return to their default values. LSBfirstSerial port communicationLSB or MSB first. MSB first. LSB first. Address ncrementControls address increment mode for multibyte register access. 0 = address decrement. 1 = address increment. SDO activewire SPI select. 0 = SDIO operates as bidirectional input/output.The SDO signal is disabled. 1 = SDIO operates as an input only.The SDO signal is active. SDO activeThis bit is a mirror of Bit 4 in Register 0x Address incrementThis bit is a mirror of Bit 5 in Register 0x LSBfirstThis bit is a mirror of Bit 6 in Register 0x ResetThis bit is a mirror of Bit 7 in Register 0x Chip ype[3:0]Die evision[3:0]Die revision number0000 ��Rev. | Page of Data Sheet NameAddress (Hex)BitBit NameDescriptionDefault Filter Strobe[7:0]Load oefficients[1:0]When toggled from 0 to 1, the filter coefficients in configuration egister 0x0011 through Register 0x0027 are loadedinto the IIR filter. Filter onfiguration 0x0011[7:0]Coefficient[7:0]Programmable filter coefficients.0xC0 0x0012[7:0]Coefficient[7:0]Programmable filter coefficients.0x0F 0x0013[7:0]Coefficient[7:0]Programmable filter coefficients.0x1D 0x0014[7:0]Coefficient[7:0]Programmable filter coefficients.0xD7 0x0015[7:0]Coefficient[7:0]Programmable filter coefficients.0xC0 0x0016 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F 2 0x0017[7:0]Coefficient[7:0]Programmable filter coefficients.0xC0 0x0018[7:0]Coefficient[7:0]Programmable filter coefficients.0x0F 0x0019[7:0]Coefficient[7:0]Programmable filter coefficients.0x1D 0x001A[7:0]Coefficient[7:0]Programmable filter coefficients.0x97 0x001B[7:0]Coefficient[7:0]Programmable filter coefficients.0x7E 0x001C[7:0]Coefficient[7:0]Programmable filter coefficients.0x88 0x001D[7:0]Coefficient[7:0]Programmable filter coefficients.0xC0 0x001E[7:0]Coefficient[7:0]Programmable filter coefficients.0x0F 0x001F [7:0] Coefficient[7:0] Programmable filter coefficients. 0xC0 2 0x0020[7:0]Coefficient[7:0]Programmable filter coefficients.0x0F 0x0021[7:0]Coefficient[7:0]Programmable filter coefficients.0xC0 0x0022 [7:0] Coefficient[7:0] Programmable filter coefficients. 0x0F 2 0x0023[7:0]Coefficient[7:0]Programmable filter coefficients.0x00 0x0024[7:0]Coefficient[7:0]Programmable filter coefficients.0xE0 0x0025[7:0]Coefficient[7:0]Programmable filter coefficients.0x23 0x0026[7:0]Coefficient[7:0]Programmable filter coefficients.0x02 0x0027[7:0]Coefficient[7:0]Programmable filter coefficients.0x24 Analog Pin Configuration0x0028INP gain1 = only the INP input signal is sampled. An additional 6 dB of gain is applied to the signal path. Clock source select0 = device is configured to generate a clock if a crystal or resonator is placed between the XOUT and CLKIN pins. 1 = device is configured to accept a CMOS level clock on the CLKIN pin. The internal XOUTdriver is disabled. Sync Control0x0029SYNCO output enable1 = enables the SYNCO output pad driver. SYNCO invert1 = inverts the SYNCO signal. [3:0] SYNCO edge select These bits select one of 16 different edge locations for the SYNCO pulse relative to the output sample window. See Figure for details. 1101 Demodontrol0x002AHASE1 = delays the phase between the RCLK output and the strobe controlling the mixing signal. See Figure for details. Mixer enable1 = the last sample that is taken while RCLK is active remains held while RCLK is inactive. RCLK select0 = sends the SDO signal to the output driver of Pin 13. 1 = sends the RCLK signal to the output driver of Pin 13. [2:0]VOCM select000 = set the VOCM pin to V/2. Low power mode. 001 = se the external reference to drive VOCM. 010 = et the VOCM pin to V/2. Fast settling mode. 101 = et the VOCM pin to 1.2 ��Rev. | Page of Data Sheet NameAddress (Hex)BitBit NameDescriptionDefault Clock Configuration0x002B[4:2]CLKIN DIV[2:0]The division factor between fCLKINand f 000 = divide by 1. 001 = divide by 16. 010 = divide by 64. 100 = divide by 256. [1:0]RCLK DIV[1:0]These bits set the division factor between fand f 00 = reserved. 01 = the frequency of RCLK is f/4. 10 = the frequency of RCLK is f/8. 11 = reserved. Digital Pin Configuration0x002CRCLK/SDOoutput enable1 = RCLK/SDO output pad driver is enabled. Core Reset0x002DCore reset1 = puts the device core into reset. The values of the SPI registers are preserved. This does not initiate a boot from the EEPROM. 0 = core reset is deasserted. Checksum0x002E[7:0]Checksum value[7:0]This is the 8bit checksum calculated by the ADA2200performed on the data it reads from the EEPROM.N/A EEPROM Status0x002FChecksum failed1 = calculated checksum does not match the checksum byte read from the EEPROM.N/A Checksum passed1 = calculated checksum matches the checksum byte read from the EEPROM.N/A Boot from EEPROM complete1 = boot from the EEPROM has completed.N/A 0 = boot from the EEPROM has timed out. Wait 10,000 clock cycles after the boot is initiated to check for boot completion. NA/ means not applicable.he filter coefficients listed are the default values programmed into the filter on reset. The value read back from the registers is 0x00.Figure 33Detailed Block Diagram 1010 INP INN CLKIN XOUT VOCM RCLK/SDO OUTN OUTP VDD LPF 8 SYNCO SCLK/SCL SDIO/SDA CS/A0 CONTROLREGISTERS SPI/IMASTERRST BOOT ADA2200 0x0028[1] 0x002A[4] 0x002A[6] {000,001,010,100}÷ {1,16,64,256}CLKIN0x002B[4:2] {1,0}÷ {4,8}0x002B[0] BPFNYQ S/H VOCMGEN 0x002A[2:0] 0x002A[3] 0x002C[0] 0x0029[3:0]0x0029[5]0x0029[4] 0x0028[0] 90°0101 EN RCLK TRI SYNCGEN EN ÷32CLKINSDO12295-037 ��Rev. | Page of Data Sheet OUTLINE DIMENSIONSFigure 3416Lead Thin Shrink Small OutlinePackage[TSSOP]16)Dimensions shown in millimetersORDERING GUIDEModelTemperature RangePackage DescriptionPackage Option ADA2200RUZ40°C to +85°CLead Thin Shrink Small Outline Package [TSSOP] ADA220RUZREEL740°C to+85°CLead Thin Shrink Small Outline Package [TSSOP] ADA2200EVALZEvaluation board with EEPROM boot ADA2200SDPEVALZEvaluation board with SDPB interface option Z = RoHSCompliant Part.C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 16981 PIN 1 SEATINGPLANE 8°0° 4.504.404.30 6.40BSC 5.105.004.900.65BSC0.150.05 1.20MAX0.200.09 0.750.600.45 0.300.19 COPLANARITY0.10COMPLIANT TO JEDEC STANDARDS MO-153-AB © 2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.D122958/14(0) ��Rev. | Page of Synchronous Demodulator and ConfigurableAnalog Filter Data Sheet ADA2200 FEATURESDemodulatesignal input bandwidths to kHzProgrammable filterenables variable bandwidthsFilter tracks input carrierfrequencyProgrammable reference clock frequencyFlexiblesystem interfaceSingleended/differential signal inputs and outputsRailrail outputs directly drive analogdigital converters (ADCs) Phase detection sensitivity9.3m 剅L牭s Con晩gur慢le睩th wi牥a湤‴wi牥獥r楡l⁰ort⁩nt敲晡c攠(S偉獥amle獳⁢ootf牯m䕅PROMsV敲yow⁰ow敲 潰erati潮慴 䍌KIN ADA2200is available in a 16lead TSSOP package. Its performance is specified over the industrial temperature range of 40°C to 85°CNote that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single function of the pin, for example, CLK, when only that function is relevant.Patent ending INP INN OUTP OUTN VOCM SCLK/SCL SDIO/SDA CS/A0 RCLK/SDO VDD LPF 8 PROGRAMFILTER CLOCKGEN CONTROLREGISTERS SPI/IMASTER VCM n+1 ÷2m ÷8 90° XOUT CLKIN SYNCO GND RST BOOT ADA220012295-001 Rev.Document FeedbackInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106,Norwood, MA 020629106, U.S.A.Tel: 781.329.47002014Analog Devices, Inc. All rights reserved.Technical Supportwww.analog.com 78798081828384NUMBER OF HITSRELATIVE PHASE (Degrees)12295-109 –0.20–0.15–0.10–0.050.050.1030405060SETTLING ERROR (%)TIME (µs)12295-110 –120–906090MAGNITUDE ERROR (mV)RELATIVE PHASE (Degrees)12295-114 MAGNITUDE ERROR MAGNITUDE ERROR, OFFSET REMOVED 987654321OUTPUT NOISE (µV)TIME (Seconds)12295-112 NOISE SPECTRAL DENSITY (nV/√Hz)FREQUENCY (Hz)12295-113 CLKIN = 500kHz –1.0–0.8–0.6–0.4–0.20.20.40.60.81.0–120–906090PHASE MEASUREMENT ERROR (Degrees)RELATIVE PHASE (Degrees)12295-111 PHASE ERROR PHASE ERROR, OFFSET REMOVED