A Mekkaoui LBNL Motivation To explore the capabilities of advanced CMOS processes to address future HEP needs upgrades SLHC To have a feel of what is the best way these processes should be used to maximize ROI ID: 280387
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Slide1
ATPIX65A: presentation and very preliminary results
A.
Mekkaoui
(LBNL)Slide2
Motivation
To explore the capabilities of advanced CMOS processes to address future HEP needs (upgrades, SLHC?, )
To have a feel of what is the best way these processes should be used to maximize ROI.
To evaluate radiation hardness (mainly SEU and new damage mechanisms, if any!)
To keep abreast of the state of the art (if one can). These technologies are already considered “mainstream” for certain application segments. Slide3
Why 65nm ?
The only more advanced available processes are the TSMC 40/45 nm. (cost >>)
CERN is considering the 65nm as their next advanced process
t
o explore
Chosen for the HIPPO/POM (here at the lab)
HIPPO
: High-Speed Image Pre-Processor with Oversampling (fast CCD RO)
POM
: Processor Of
MuonsSlide4
Why TSMC?
Presently the only reliable source (twice a month thru MOSIS)
Chosen by the hippo project (we are only piggy-backing)Slide5
HIPPO Block diagram (Carl Grace)
Slide6
Pixel FE (65nm mockup)
“Simplified” FEND schematics
Not routed yet
Work in progress
C
onfig
memory: 10b triple
redudant
with auto-correction + shift register +
readback
Capabilities
(Common with hippo)
Comparator
TDAC
PreampSlide7
Region logic synthesized from FEI4
verilog
.
Neither complete nor verified.
Just to have an idea on what is possible (Thanks Dario)
Pixel size=50X100 (?)
~FEI4 AFE equivalent
Pixel region (2X2) a la FEI4 if implemented in 65nmSlide8
FEI4 2X2 REGION (100X500)
“FEI5”
2X2 REGION (
100X200
)
Ultimately the width of a pixel will limited by practical
considerations (power distribution) and not the number of transistors!
FIE4 pixel region Vs Pix65nm region
(assuming y=50u)Slide9
Snapshot of submitted array
25
m
m y cell pitch but 50
m
m bump y
picth
.
Power distribution will be major factor in the ultimate minumum dimensionsBump mask not part of the submitted layout (same size as FEI4)
Analog FE
Config
. Logic
Future
Digital
Region
nXm
pixelsSlide10
Pixel Bloc DiagramSlide11
Fend Bloc diagram
Inject Bloc
Preamp.
17fF
Feeback
cap.
Variable “
Rff
”
Single to differential+
Comparator “preamp”
Comparator
TDAC (+/- tuning)Slide12
ATPIX65A chip (16X32 array)
Pixels with
Added
Diodes
(row 11:31)
Pixels with
Added
mimcaps
(31,27,18)Slide13
Some simulation results (preamp output)
Pixels with
Added
Diodes
(row 11:31)
Pixels with
Added
mimcaps
(31,27,18)Slide14
PreampOut
Diff. out.
Qth
<
Qin
Hit Out
Diff. out.
Qth > QinHit OutSome simulation results (qin
=1ke-, 2
qth
settings)Slide15
ENC Vs Cdet
for # Preamp currentsSlide16
Preliminary test results (ENC distribution)
(analysis program still under scrutiny)
May be !Slide17
Preliminary test results (ENC distribution by column)
Column 15: few Pixels with diodes
Column 0: 4 pixels with caps!!!
Green DOT == low quality error function fit!Slide18
Preliminary test results (Threshold histogram)
Column 15: few Pixels with diodes
Column 0: 4 pixels with caps!!!
Green DOT == low quality error function fit!
s
> than FEI4
(as expected!)Slide19
Preliminary test results (Threshold distribution by
col
)
COLSlide20
Conclusions
Good very preliminary results.
No major bad surprise so far.
Absolute calibration is needed
“Parasitic” injection not according to “plan”
(new simulations needed to understand)
Seems to be a sound basis for a “real” new pixel chip.
Radiation and SEU test:
very interesting.Slide21
AREA OF ARM11 CORES
PPA
ARM1176
ARM1176
ARM1176
Process Geometry
TSMC65LP
TSMC 65GP TSMC 40G Performance (DMIPS)
603
965
1238
Performance (Coremarks)
1002
1605
2058
Frequency * (MHz)
482
772 990
Total area (mm2) 1.75
1.94 1.17
Power efficiency (DMIPS/mW)
3
6
12
Dynamic power (mW/MHz) **
0.41
0.208
0.105
Source: http://www.arm.com/products/processors/classic/arm11/arm1176.php