Manual HDL for HEP applications MarcAndré Tétrault IEEE NPSS Real Time Conference 2018 Williamsburg Overview Whatwhy High Level Synthesis HLS First contact account Signal processing design ID: 1001899
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1. Two FPGA Case Studies Comparing High Level Synthesis and Manual HDL for HEP applicationsMarc-André TétraultIEEE NPSS Real Time Conference 2018Williamsburg
2. OverviewWhat/why High Level Synthesis (HLS)First contact accountSignal processing designFlow-through event sorting engineTake home messageIEEE NPSS Real Time Conference 2018 - Williamsburg2
3. Hardware Description Language (VHDL)process(clk)begin if (clk'event and clk = '1')then q_ResetBLine <= Control(1) xor Control(2); q_MeanBLine <= Control(2) xor Control(c_Size - 1); if(q_ResetBaseline = '1')then q_MeanAcc <= "00" & i_EventStream; elsif(q_MeanBaseline = '1') then q_MeanAcc <= q_MeanAcc + i_EventStream; end if; end if;end process;High Level Synthesis (C/C++)int BaseLineMean(int Samples[], int ReturnSamples[]){ int Mean = 0; for(int x= 0 ; x < SAMPLE_COUNT; x++) { if(x < 4) Mean += Samples[x]; ReturnSamples[x] = Samples[x]; } Mean >>= 2; // divide by 4 return Mean;}What is High Level SynthesisAdditional declarations and flow control sectionsIEEE NPSS Real Time Conference 2018 - Williamsburg3Example process:Average of first 4 samples Sample Stream10 bit8 bit MSBFlow ControlAdditional directives to HLS compiler
4. Appropriate for HEP designs?Tutorial examples sound like a yesWhat about real designs?Compare with manual HDL? Recreate parts of past designsExtensive logs, reports and code availableDesign time in man-hoursLogic resource usageThroughputFirst contact accountGood prior FPGA/VHDL experienceNo prior HLS experience whatsoever (only tutorials)IEEE NPSS Real Time Conference 2018 - Williamsburg4
5. Project 1 : Crystal Identification for PETTetrault et al, TNS 2010IEEE NPSS Real Time Conference 2018 - Williamsburg5DetectorLv1 TriggerSample ProcessingLv2 TriggerADCDownstream consumers…
6. Design MethodologyIEEE NPSS Real Time Conference 2018 - Williamsburg6MatlabAlgorithmHigh Level ModelLogic Friendly ModelVHDLVHDLTest BenchFixed point fine tuningVerificationDivergence Evaluation14 man-days~2-3 weeks
7. Design MethodologyIEEE NPSS Real Time Conference 2018 - Williamsburg7MatlabC/C++AlgorithmHigh Level ModelLogic Friendly ModelVHDLVHDLTest BenchFixed point fine tuningVerificationDivergence EvaluationAlgorithmHigh Level ModelLogic Friendly ModelHLSTest Bench?Fixed point fine tuningVerificationDivergence Evaluation8 man days to rewrite from originalLikely same 2-3 weeks in real situationSynthesis
8. Project 1: Results Manual HDLHLS Virtex-II ProZynq 7000Zynq 7000Flip Flops176217363910LUT181614383542RAM Blocks332Multipliers232324Event Interval36 clocks36 clocks36 clocksLatency252 clocks252 clocks300 clocksClock period6.78 ns5.3 ns10.7 nsIEEE NPSS Real Time Conference 2018 - Williamsburg8
9. Project 1:Lessons learnedTiming not reached, larger design, but…Learned new strategies at the workshop, to be attemptedTime savingHard to do exact comparison, but still consider HLS fasterNo duplicate test bench to writeFirst HLS design, learned on the fly, some trial and errorPrior FPGA experience very advantageousExisting intuition about synthesis-friendly design entryEasier to identify and fix bottlenecks and poor synthesis attemptsIEEE NPSS Real Time Conference 2018 - Williamsburg9
10. Project 2: Flow-Through Event SorterFirst version in 2005Virtex2 Pro100 MHz700k events/sec, list depth of 112 events5 man-daysSecond version in 2008Virtex-5/6/7300 MHz1M events/sec, memory depth of 290 events5 man-days (pipeline re-alignment)IEEE NPSS Real Time Conference 2018 - Williamsburg10Shift list and insert when smallerTetrault et al, TNS 2010
11. Project 2: Flow-Through Event SorterCircular memory list3-stage PipelineOne special case when event leaving sorter at bottom of the listIEEE NPSS Real Time Conference 2018 - Williamsburg11Comp N-2Write in N-3Read N-1Comp N-1Write in N-2Read NComp NWrite in N-1Read 0Pass to NextWrite in NRead 1Comp 1Write in 0Read 2Comp 2Write in 1
12. Project 2: resultsItems to improveExplicit pipeline in C code Harder to read intentHow to wrap loop on itself without reinitialization?Needs 8 clocks to start the pipeline every timeStill looking for potential directivesBut… Manual HDLHLS Zynq 7000Zynq 7000Flip Flops187522LUT75471RAM Blocks12Sorting Cycle100 clocks108 clocksMax Frequency300 MHz300 MHzMan days5 days1-2 daysIEEE NPSS Real Time Conference 2018 - Williamsburg12
13. Project 2: Lessons LearnedVirtex-2 Pro to Virtex-5/6/7 Migration135 MHz to 300 MHzMultiplier primitive change (register stages)5 days with debug (same as initial design!)With HLS, tool adjusts the pipeline automaticallyFrom 135 MHz to 300 MHz in one setting changeNo modifications to the codeExpect easier migration between generations/technologyIEEE NPSS Real Time Conference 2018 - Williamsburg13
14. ConclusionHLS workflow is compatible with the two use casesStrong code reuse potentialOptimization : prior FPGA experience is very helpfulUnderstanding the reports and implications is crucialHLS designs have larger logic footprint… but better experience with the tool have good chances to improve thisIEEE NPSS Real Time Conference 2018 - Williamsburg14
15. Thank you!Questions?