The RISC-V Processor Hakim Weatherspoon - PowerPoint Presentation

1. The RISC-V ProcessorHakim WeatherspoonCS 3410Computer ScienceCornell University[Weatherspoon, Bala, Bracy, and Sirer]

2. Announcements Make sure to go to your Lab Section this weekCompleted Proj1 due Friday, Feb 15thNote, a Design Document is due when you submit Proj1 final circuitWork aloneBUT use your resourcesLab Section, Piazza.com, Office HoursClass notes, book, Sections, CSUGLab2

3. 3AnnouncementsCheck online syllabus/schedule http://www.cs.cornell.edu/Courses/CS3410/2019sp/scheduleSlides and Reading for lecturesOffice HoursPictures of all TAsProject and Reading AssignmentsDates to keep in MindPrelims: Tue Mar 5th and Thur May 2nd Proj 1: Due next Friday, Feb 15thProj3: Due before Spring breakFinal Project: Due when final will be Feb 16thSchedule is subject to change

4. 4Collaboration, Late, Re-grading Policies“White Board” Collaboration PolicyCan discuss approach together on a “white board”Leave, watch a movie such as Black Lightening, then write up solution independentlyDo not copy solutionsLate PolicyEach person has a total of five “slip days”Max of two slip days for any individual assignmentSlip days deducted first for any late assignment, cannot selectively apply slip daysFor projects, slip days are deducted from all partners 25% deducted per day late after slip days are exhaustedRegrade policySubmit written request within a week of receiving score

5. Announcements5Level Up (optional enrichment)Teaches CS students tools and skills needed in their coursework as well as their career, such as Git, Bash Programming, study strategies, ethics in CS, and even applying to graduate school.Thursdays at 7-8pm in 310 Gates Hall, starting this weekhttp://www.cs.cornell.edu/courses/cs3110/2019sp/levelup/

6. 6Big Picture: Building a ProcessorPCimmmemorytargetoffsetcmpcontrol=?new pcmemorydindoutaddrregisterfileinstextendA single cycle processoralu+4+4

7. 7Goal for the next few lecturesUnderstanding the basics of a processorWe now have the technology to build a CPU!Putting it all together:Arithmetic Logic Unit (ALU)Register FileMemorySRAM: cacheDRAM: main memoryRISC-V Instructions & how they are executed7

8. 8PCimmmemorytargetoffsetcmpcontrol=?new pcmemorydindoutaddrregisterfileinstextendaluRISC-V Register File+4+4A single cycle processor

9. 9RISC-V Register FileRISC-V register file32 registers, 32-bits each x0 wired to zeroWrite port indexed via RWon falling edge when WE=1Read ports indexed via RA, RBDual-Read-PortSingle-Write-Port32 x 32 Register FileQAQBDWRWRARBWE3232321555

10. RISC-V Register FileRISC-V register file32 registers, 32-bits each x0 wired to zeroWrite port indexed via RWon falling edge when WE=1Read ports indexed via RA, RBRISC-V register fileNumbered from 0 to 31Can be referred by number: x0, x1, x2, … x31Convention, each register also has a name: x10 – x17  a0 – a7, x28 – x31  t3 – t6ABWRWRARBWE32323215558x0x1…x31

11. 11PCimmmemorytargetoffsetcmpcontrol=?new pcmemorydindoutaddrregisterfileinstextendaluRISC-V Memory+4+4A single cycle processor

12. 12RISC-V Memory32-bit address32-bit data (but byte addressed)Enable + 2 bit memory control (mc)00: read word (4 byte aligned)01: write byte10: write halfword (2 byte aligned)11: write word (4 byte aligned)memory32addr2mc3232EDinDout0x000fffff. . .0x0000000b0x0000000a0x000000090x000000080x000000070x000000060x000000050x000000040x000000030x000000020x000000010x000000000x051 byteaddress

13. 13PCimmmemorytargetoffsetcmpcontrol=?new pcmemorydindoutaddrregisterfileinstextendaluPutting it all together: Basic Processor+4+4A single cycle processor

14. Need a programStored program computerArchitecturesvon Neumann architectureHarvard (modified) architectureTo make a computer14

15. Need a programStored program computer(a Universal Turing Machine)Architecturesvon Neumann architectureHarvard (modified) architectureTo make a computer15

16. 16A RISC-V CPU with a (modified) Harvard architectureModified: instructions & data in common address space, separate instr/data caches can be accessed in parallelCPURegistersDataMemorydata, address, controlALUControl001000000010010000001000010000100...ProgramMemory101000100001011000001100100010101...Putting it all together: Basic Processor

17. 17A processor executes instructionsProcessor has some internal state in storage elements (registers)A memory holds instructions and data(modified) Harvard architecture: separate insts and datavon Neumann architecture: combined inst and dataA bus connects the twoWe now have enough building blocks to build machines that can perform non-trivial computational tasksTakeaway

18. Next Goal18How to program and execute instructions on a RISC-V processor?

19. 19Instruction ProcessingA basic processor fetchesdecodesexecutes one instruction at a time0010000000000010000000000000101000100000000000010000000000000000000000000010001000011000001010105ALU55controlReg.FilePCProgMeminst+4DataMemInstructions: stored in memory, encoded in binary

20. Levels of Interpretation: Instructions20High Level LanguageC, Java, Python, ADA, …Loops, control flow, variablesfor (i = 0; i < 10; i++) printf(“go cucs”); main: addi x2, x0, 10 addi x1, x0, 0 loop: slt x3, x1, x2 ...Assembly LanguageNo symbols (except labels)One operation per statement“human readable machine language”Machine LanguageBinary-encoded assemblyLabels become addressesThe language of the CPUALU, Control, Register File, …Machine Implementation (Microarchitecture)Instruction Set Architecture00000000101000010000000000010011001000000000000100000000000100000000000000100010000110000010101010 x2 x0 op=addi

21. Different CPU architectures specify different instructionsTwo classes of ISAsReduced Instruction Set Computers (RISC) IBM Power PC, Sun Sparc, MIPS, AlphaComplex Instruction Set Computers (CISC) Intel x86, PDP-11, VAXAnother ISA classification: Load/Store ArchitectureData must be in registers to be operated on For example: array[x] = array[y] + array[z] 1 add ? OR 2 loads, an add, and a store ?Keeps HW simple  many RISC ISAs are load/storeInstruction Set Architecture (ISA)21

22. Takeaway22A RISC-V processor and ISA (instruction set architecture) is an example a Reduced Instruction Set Computers (RISC) where simplicity is key, thus enabling us to build it!!

23. Next Goal23How are instructions executed? What is the general datapath to execute an instruction?

24. Five Stages of RISC-V Datapath245ALU55controlReg.FilePCProg.Meminst+4DataMemFetchDecodeExecuteMemoryWBA single cycle processor – this diagram is not 100% spatial

25. Basic CPU execution loopInstruction FetchInstruction DecodeExecution (ALU)Memory AccessRegister WritebackFive Stages of RISC-V Datapath25

26. Stage 1: Instruction Fetch265ALU55controlReg.FilePCProg.Meminst+4DataMemFetch 32-bit instruction from memoryIncrement PC = PC + 4FetchDecodeExecuteMemoryWB

27. Stage 2: Instruction Decode275ALU55controlReg.FilePCProg.Meminst+4DataMemGather data from the instructionRead opcode; determine instruction type, field lengthsRead in data from register file (0, 1, or 2 reads for jump, addi, or add, respectively)FetchDecodeExecuteMemoryWB

28. Stage 3: Execution (ALU)285ALU55controlReg.FilePCProg.Meminst+4DataMemUseful work done here (+, -, *, /), shift, logic operation, comparison (slt)Load/Store? lw x2, x3, 32  Compute addressFetchDecodeExecuteMemoryWB

29. Stage 4: Memory Access295ALU55controlReg.FilePCProg.Meminst+4DataMemUsed by load and store instructions onlyOther instructions will skip this stageR/Waddr Data Data FetchDecodeExecuteMemoryWB

30. Stage 5: Writeback305ALU55controlReg.FilePCProg.Meminst+4DataMemWrite to register fileFor arithmetic ops, logic, shift, etc, load. What about stores?Update PCFor branches, jumpsFetchDecodeExecuteMemoryWB

31. Takeaway31The datapath for a RISC-V processor has five stages:Instruction FetchInstruction DecodeExecution (ALU)Memory AccessRegister WritebackThis five stage datapath is used to execute all RISC-V instructions

32. Next Goal32Specific datapaths RISC-V Instructions

33. 33RISC-V Design PrinciplesSimplicity favors regularity32 bit instructionsSmaller is fasterSmall register fileMake the common case fastInclude support for constantsGood design demands good compromisesSupport for different type of interpretations/classes

34. 34Instruction TypesArithmeticadd, subtract, shift left, shift right, multiply, divideMemoryload value from memory to a registerstore value to memory from a registerControl flowconditional jumps (branches)jump and link (subroutine call)Many other instructions are possiblevector add/sub/mul/div, string operations manipulate coprocessorI/O

35. 35RISC-V Instruction TypesArithmetic/LogicalR-type: result and two source registers, shift amountI-type: result and source register, shift amount in 16-bit immediate with sign/zero extensionU-type: result register, 16-bit immediate with sign/zero extensionMemory AccessI-type for loads and S-type for storesload/store between registers and memoryword, half-word and byte operationsControl flowU-type: jump-and-linkI-type: jump-and-link registerS-type: conditional branches: pc-relative addresses

36. 36RISC-V instruction formatsAll RISC-V instructions are 32 bits long, have 4 formatsR-typeI-typeS-typeU-type funct7rs2rs1funct3rdop7 bits5 bits5 bits3 bits5 bits7 bitsimmrs1funct3rdop12 bits5 bits3 bits5 bits7 bitsimmrs2rs1funct3immop7 bits5 bits5 bits3 bits5 bits7 bitsimmrdop20 bits5 bits7 bits

37. R-Type (1): Arithmetic and Logic37funct7rs2rs1funct3rdop7 bits5 bits5 bits3 bits5 bits7 bitsopfunct3mnemonicdescription0110011000ADD rd, rs1, rs2R[rd] = R[rs1] + R[rs2]0110011000SUB rd, rs1, rs2R[rd] = R[rs1] – R[rs2]0110011110OR rd, rs1, rs2R[rd] = R[rs1] | R[rs2]0110011100XOR rd, rs1, rs2R[rd] = R[rs1]  R[rs2]00000000011001000100001000110011

38. 38Arithmetic and LogicFetchDecodeExecuteMemoryWBskipALUPCProg.Mem+4555Reg.Filecontrol

39. 39R-Type (2): Shift Instructionsfunct7rs2rs1funct3rdop7 bits5 bits5 bits3 bits5 bits7 bitsopfunct3mnemonicdescription0110011001SLL rd, rs1, rs2R[rd] = R[rs1] << R[rs2]0110011101SRL rd, rs1, rs2R[rd] = R[rs1] >>> R[rs2] (zero ext.)0110011101SRA rd, rs1, rs2R[rd] = R[rt] >>> R[rs2] (sign ext.)0000000001100010000101000011011

40. 40ShiftDecodeExecuteWBMemoryskipALUPCProg.Mem+4555Reg.FilecontrolFetch

41. 41I-Type (1): Arithmetic w/ immediatesimmrs1funct3rdop12 bits5 bits3 bits5 bits7 bitsopfunct3mnemonicdescription0010011000ADDI rd, rs1, immR[rd] = R[rs1] + imm0010011111ANDI rd, rs1, immR[rd] = R[rs1] & zero_extend(imm)0010011110ORI rd, rs1, immR[rd] = R[rs1] | zero_extend(imm)00000000010100101000001010010011

42. 42Arithmetic w/ immediatesFetchDecodeExecuteMemoryWBskipALUPCProg.Mem+4555Reg.Filecontrolimmextendshamt1612

43. 43U-Type (1): Load Upper Immediate”“immrdop20 bits5 bits7 bitsopmnemonicdescription0110111LUI rd, immR[rd] = imm << 1600000000000000000101001010110111

44. 44Load Upper ImmediateFetchDecodeExecuteMemoryWBskipALUPCProg.Mem+4555Reg.Filecontrolimmextendshamt1612160x50000

45. 45RISC-V Instruction TypesArithmetic/LogicalR-type: result and two source registers, shift amountI-type: result and source register, shift amount in 16-bit immediate with sign/zero extensionU-type: result register, 16-bit immediate with sign/zero extensionMemory AccessI-type for loads and S-type for storesload/store between registers and memoryword, half-word and byte operationsControl flowU-type: jump-and-linkI-type: jump-and-link registerS-type: conditional branches: pc-relative addresses✔

46. 46RISC-V Instruction TypesArithmetic/LogicalR-type: result and two source registers, shift amountI-type: result and source register, shift amount in 16-bit immediate with sign/zero extensionU-type: result register, 16-bit immediate with sign/zero extensionMemory AccessI-type for loads and S-type for storesload/store between registers and memoryword, half-word and byte operationsControl flowU-type: jump-and-linkI-type: jump-and-link registerS-type: conditional branches: pc-relative addresses✔

47. Summary47We have all that it takes to build a processor!Arithmetic Logic Unit (ALU)Register FileMemoryRISC-V processor and ISA is an example of a Reduced Instruction Set Computers (RISC)Simplicity is key, thus enabling us to build it!We now know the data path for the MIPS ISA:register, memory and control instructions