2 Sequential Logic Counters and Registers Counters Introduction Counters Asynchronous Ripple Counters Asynchronous Counters with MOD number lt 2 n Asynchronous Down Counters Cascading Asynchronous Counters ID: 1024977
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1. 1Logical Organization of Computers
2. 2Sequential Logic Counters and RegistersCountersIntroduction: CountersAsynchronous (Ripple) CountersAsynchronous Counters with MOD number < 2nAsynchronous Down CountersCascading Asynchronous Counters
3. 3Sequential Logic Counters and RegistersSynchronous (Parallel) CountersUp/Down Synchronous CountersDesigning Synchronous CountersDecoding A CounterCounters with Parallel Load
4. 4Sequential Logic Counters and RegistersRegistersIntroduction: RegistersSimple RegistersRegisters with Parallel LoadUsing Registers to implement Sequential CircuitsShift RegistersSerial In/Serial Out Shift RegistersSerial In/Parallel Out Shift RegistersParallel In/Serial Out Shift RegistersParallel In/Parallel Out Shift Registers
5. 5Sequential Logic Counters and RegistersBidirectional Shift RegistersAn Application – Serial AdditionShift Register CountersRing CountersJohnson CountersRandom-Access Memory (RAM)
6. 6Introduction: CountersCounters are circuits that cycle through a specified number of states.Two types of counters:synchronous (parallel) countersasynchronous (ripple) countersRipple counters allow some flip-flop outputs to be used as a source of clock for other flip-flops.Synchronous counters apply the same clock to all flip-flops.
7. 7Asynchronous (Ripple) CountersAsynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse.Also known as ripple counters, as the input clock pulse “ripples” through the counter – cumulative delay is a drawback.n flip-flops a MOD (modulus) 2n counter. (Note: A MOD-x counter cycles through x states.)Output of the last flip-flop (MSB) divides the input clock frequency by the MOD number of the counter, hence a counter is also a frequency divider.
8. 8Asynchronous (Ripple) CountersExample: 2-bit ripple binary counter.Output of one flip-flop is connected to the clock input of the next more-significant flip-flop.KJKJHIGHQ0Q1Q0FF1FF0CLKCCTiming diagram00 01 10 11 00 ... 4321CLKQ0Q0Q11111000000
9. 9Asynchronous (Ripple) CountersExample: 3-bit ripple binary counter.KJKJQ0Q1Q0FF1FF0CCKJQ1CFF2Q2CLKHIGH4321CLKQ0Q11111000000876511001100Q2000011110Recycles back to 0
10. 10Asynchronous (Ripple) CountersPropagation delays in an asynchronous (ripple-clocked) binary counter.If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented!4321CLKQ0Q1Q2tPLH(CLK to Q0)tPHL (CLK to Q0)tPLH (Q0 to Q1)tPHL (CLK to Q0)tPHL (Q0 to Q1)tPLH (Q1 to Q2)
11. 11Asynchronous (Ripple) CountersExample: 4-bit ripple binary counter (negative-edge triggered).KJKJQ1Q0FF1FF0CCKJCFF2Q2CLKHIGHKJCFF3Q3CLK12345678910111213141516Q0Q1Q2Q3
12. 12Asyn. Counters with MOD no. < 2nStates may be skipped resulting in a truncated sequence.Technique: force counter to recycle before going through all of the states in the binary sequence.Example: Given the following circuit, determine the counting sequence (and hence the modulus no.)KJQQCLKCLRKJQQCLKCLRKJQQCLKCLRCBABCAll J, K inputs are 1 (HIGH).
13. 13Asyn. Counters with MOD no. < 2nExample (cont’d):KJQQCLKCLRKJQQCLKCLRKJQQCLKCLRCBABCAll J, K inputs are 1 (HIGH).AB12CNANDOutput103456789101112ClockMOD-6 counter produced by clearing (a MOD-8 binary counter) when count of six (110) occurs.
14. 14Asyn. Counters with MOD no. < 2nExample (cont’d): Counting sequence of circuit (in CBA order).ABCNANDOutput10123456789101112Clock111000001110101100010011Temporary stateCounter is a MOD-6 counter.000100010110001101000100
15. 15Asyn. Counters with MOD no. < 2nExercise: How to construct an asynchronous MOD-5 counter? MOD-7 counter? MOD-12 counter?Question: The following is a MOD-? counter?KJQQCLRCBACDEFAll J = K = 1.KJQQCLRKJQQCLRKJQQCLRKJQQCLRKJQQCLRDEF
16. 16Asyn. Counters with MOD no. < 2nDecade counters (or BCD counters) are counters with 10 states (modulus-10) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.).Design an asynchronous decade counter.DCLKHIGHKJCCLRQKJCCLRQCKJCCLRQBKJCCLRQA(A.C)'
17. 17Asyn. Counters with MOD no. < 2nAsynchronous decade/BCD counter (cont’d).DC12BNAND output345678910Clock11ADCLKHIGHKJCCLRQKJCCLRQCKJCCLRQBKJCCLRQA(A.C)'00001000010011000010101001101110000110010000
18. 18Asynchronous Down CountersSo far we are dealing with up counters. Down counters, on the other hand, count downward from a maximum value to zero, and repeat.Example: A 3-bit binary (MOD-23) down counter. KJKJQ1Q0CCKJCQ2CLK1QQ'QQ'QQ'QQ'3-bit binary up counter3-bit binary down counter1KJKJQ1Q0CCKJCQ2CLKQQ'QQ'QQ'QQ'
19. 19Asynchronous Down CountersExample: A 3-bit binary (MOD-8) down counter. 4321CLKQ0Q11110001000876511001010Q21101100000010001110100111001101011KJKJQ1Q0CCKJCQ2CLKQQ'QQ'QQ'QQ'
20. 20Cascading Asynchronous CountersLarger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters.Connect last-stage output of one counter to the clock input of next counter so as to achieve higher-modulus operation.Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter.KJKJQ1Q0CCCLKQQ'QQ'QQ'KJKJQ3Q2CCKJCQ4QQ'QQ'QQ'QQ'Modulus-4 counterModulus-8 counter
21. 21Cascading Asynchronous CountersExample: A 6-bit binary counter (counts from 0 to 63) constructed from two 3-bit counters. 3-bit binary counter3-bit binary counterCount pulseA0 A1 A2A3 A4 A5
22. 22Cascading Asynchronous CountersIf counter is a not a binary counter, requires additional output.Example: A modulus-100 counter using two decade counters.CLKDecade counterQ3 Q2 Q1 Q0 CCTENTC1Decade counterQ3 Q2 Q1 Q0 CCTENTCfreqfreq/10freq/100TC = 1 when counter recycles to 0000
23. 23Synchronous (Parallel) CountersSynchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse.We can design these counters using the sequential logic design process (covered in Lecture #12).Example: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).01001011
24. 24Synchronous (Parallel) CountersExample: 2-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J,K inputs).TA1 = A0TA0 = 11KJKJA1A0CCCLKQQ'QQ'QQ'
25. 25Synchronous (Parallel) CountersExample: 3-bit synchronous binary counter (using T flip-flops, or JK flip-flops with identical J, K inputs).TA2 = A1.A0A2A1A011TA1 = A0TA0 = 1A2A1A01111A2A1A011111111
26. 26Synchronous (Parallel) CountersExample: 3-bit synchronous binary counter (cont’d).TA2 = A1.A0 TA1 = A0 TA0 = 11A2CPA1A0KQJKQJKQJ
27. 27Synchronous (Parallel) CountersNote that in a binary counter, the nth bit (shown underlined) is always complemented whenever 011…11 100…00 or 111…11 000…00Hence, Xn is complemented whenever Xn-1Xn-2 ... X1X0 = 11…11.As a result, if T flip-flops are used, then TXn = Xn-1 . Xn-2 . ... . X1 . X0
28. 28Synchronous (Parallel) CountersExample: 4-bit synchronous binary counter. TA3 = A2 . A1 . A0 TA2 = A1 . A0 TA1 = A0 TA0 = 1 1KJKJA1A0CCCLKQQ'QQ'QQ'KJA2CQQ'KJA3CQQ'A1.A0A2.A1.A0
29. 29Synchronous (Parallel) CountersExample: Synchronous decade/BCD counter.T0 = 1T1 = Q3'.Q0T2 = Q1.Q0T3 = Q2.Q1.Q0 + Q3.Q0
30. 30Synchronous (Parallel) CountersExample: Synchronous decade/BCD counter (cont’d).T0 = 1T1 = Q3'.Q0T2 = Q1.Q0T3 = Q2.Q1.Q0 + Q3.Q0 1Q1Q0CLKTCQQ'QQ'Q2Q3TCQQ'QQ'TCQQ'QQ'TCQQ'QQ'
31. 31Up/Down Synchronous CountersUp/down synchronous counter: a bidirectional counter that is capable of counting either up or down.An input (control) line Up/Down (or simply Up) specifies the direction of counting.Up/Down = 1 Count upwardUp/Down = 0 Count downward
32. 32Up/Down Synchronous CountersExample: A 3-bit up/down synchronous binary counter.TQ0 = 1TQ1 = (Q0.Up) + (Q0'.Up' )TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )Up counterTQ0 = 1TQ1 = Q0TQ2 = Q0.Q1Down counterTQ0 = 1TQ1 = Q0’TQ2 = Q0’.Q1’
33. 33Up/Down Synchronous CountersExample: A 3-bit up/down synchronous binary counter (cont’d).TQ0 = 1TQ1 = (Q0.Up) + (Q0'.Up' )TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )1Q1Q0CLKTCQQ'QQ'TCQQ'QQ'TCQQ'QQ'UpQ2
34. 34Designing Synchronous CountersCovered in Lecture #12.Example: A 3-bit Gray code counter (using JK flip-flops).100000001101111110011010
35. 35Designing Synchronous Counters3-bit Gray code counter: flip-flop inputs.0 100 01 11 10Q2Q1Q0XXXX1JQ2 = Q1.Q0'0 100 01 11 10Q2Q1Q0XXXX1KQ2 = Q1'.Q0'0 100 01 11 10Q2Q1Q0XXXX1JQ1 = Q2'.Q00 100 01 11 10Q2Q1Q0XXXX1KQ1 = Q2.Q00 100 01 11 10Q2Q1Q0XXXX1JQ0 = Q2.Q1 + Q2'.Q1'= (Q2 Q1)'10 100 01 11 10Q2Q1Q0XXXX11KQ0 = Q2.Q1' + Q2'.Q1= Q2 Q1
36. 36Designing Synchronous Counters3-bit Gray code counter: logic diagram. JQ2 = Q1.Q0' JQ1 = Q2'.Q0 JQ0 = (Q2 Q1)' KQ2 = Q1'.Q0' KQ1 = Q2.Q0 KQ0 = Q2 Q1Q1Q0CLKQ2JCQQ'KJCQQ'KJCQQ'KQ2'Q0'Q1'
37. 37Decoding A CounterDecoding a counter involves determining which state in the sequence the counter is in.Differentiate between active-HIGH and active-LOW decoding.Active-HIGH decoding: output HIGH if the counter is in the state concerned.Active-LOW decoding: output LOW if the counter is in the state concerned.
38. 38Decoding A CounterExample: MOD-8 ripple counter (active-HIGH decoding).A'B'C'123456789ClockHIGH only on count of ABC = 000A'B'CHIGH only on count of ABC = 001A'BC'HIGH only on count of ABC = 010100ABCHIGH only on count of ABC = 111...
39. 39Decoding A CounterExample: To detect that a MOD-8 counter is in state 0 (000) or state 1 (001).A'B'123456789ClockHIGH only on count of ABC = 000 or ABC = 001100Example: To detect that a MOD-8 counter is in the odd states (states 1, 3, 5 or 7), simply use C.C123456789ClockHIGH only on count of odd states100A'B'C'A'B'C
40. 40Counters with Parallel LoadCounters could be augmented with parallel load capability for the following purposes:To start at a different stateTo count a different sequenceAs more sophisticated register with increment/decrement functionality.
41. 41Counters with Parallel LoadDifferent ways of getting a MOD-6 counter:Count = 1Load = 0CPI4 I3 I2 I1 Count = 1Clear = 1CPA4 A3 A2 A1 Inputs = 0Load(a) Binary states 0,1,2,3,4,5.I4 I3 I2 I1 A4 A3 A2 A1 Inputs have no effectClear(b) Binary states 0,1,2,3,4,5.I4 I3 I2 I1 Count = 1Clear = 1CPA4 A3 A2 A1 0 0 1 1Load(d) Binary states 3,4,5,6,7,8.I4 I3 I2 I1 Count = 1Clear = 1CPA4 A3 A2 A1 1 0 1 0LoadCarry-out(c) Binary states 10,11,12,13,14,15.
42. 42Counters with Parallel Load4-bit counter with parallel load.
43. 43Introduction: RegistersAn n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information.The flip-flops store the information while the gates control when and how new information is transferred into the register.Some functions of register:retrieve data from registerstore/load new data into register (serial or parallel)shift the data within register (left or right)
44. 44Simple RegistersNo external gates.Example: A 4-bit register. A new 4-bit data is loaded every clock cycle.A3CPA1A0DQDQQDA2DQI3I1I0I2
45. 45Registers With Parallel LoadInstead of loading the register at every clock pulse, we may want to control when to load.Loading a register: transfer new information into the register. Requires a load control input.Parallel loading: all bits are loaded simultaneously.
46. 46Registers With Parallel LoadA0CLKDQLoadI0A1DQA2DQA3DQCLEARI1I2I3Load'.A0 + Load. I0
47. 47Using Registers to implement Sequential CircuitsA sequential circuit may consist of a register (memory) and a combinational circuit.RegisterCombin-ational circuitClockInputsOutputsNext-state valueThe external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit.The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices.
48. 48Using Registers to implement Sequential CircuitsExample 1: A1+ = S m(4,6) = A1.x' A2+ = S m(1,2,5,6) = A2.x' + A2'.x = A2 x y = S m(3,7) = A2.x A1A2xyA1.x'A2x
49. 49Using Registers to implement Sequential CircuitsExample 2: Repeat example 1, but use a ROM.ROM truth tableA1A2xy8 x 3 ROM
50. 50Shift RegistersAnother function of a register, besides storage, is to provide for data movements.Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses.
51. 51Shift RegistersBasic data movement in shift registers (four bits are used for illustration).Data inData out(a) Serial in/shift right/serial outData inData out(b) Serial in/shift left/serial outData inData out(c) Parallel in/serial outData outData in(d) Serial in/parallel outData outData in(e) Parallel in / parallel out(f) Rotate right(g) Rotate left
52. 52Serial In/Serial Out Shift RegistersAccepts data serially – one bit at a time – and also produces output serially.Q0CLKDCQQ1Q2Q3Serial data inputSerial data outputDCQDCQDCQ
53. 53Serial In/Serial Out Shift RegistersApplication: Serial transfer of data from one register to another.Shift register AShift register BSISISOSOClockShift controlCPWordtimeT1T2T3T4CPClockShift control
54. 54Serial In/Serial Out Shift RegistersSerial-transfer example.
55. 55Serial In/Parallel Out Shift RegistersAccepts data serially.Outputs of all stages are available simultaneously.Q0CLKDCQQ1DCQQ2DCQQ3DCQData inputDCCLKData inputQ0Q1Q2Q3SRG 4Logic symbol
56. 56Parallel In/Serial Out Shift RegistersBits are entered simultaneously, but output is serial.D0CLKDCQD1DCQD2DCQD3DCQData inputQ0Q1Q2Q3Serial data outSHIFT/LOADSHIFT.Q0 + SHIFT'.D1
57. 57Parallel In/Serial Out Shift RegistersBits are entered simultaneously, but output is serial.Logic symbolCCLKSHIFT/LOADD0D1D2D3SRG 4Serial data outData in
58. 58Parallel In/Parallel Out Shift RegistersSimultaneous input and output of all data bits.Q0CLKDCQQ1DCQQ2DCQQ3DCQParallel data inputsD0D1D2D3Parallel data outputs
59. 59Bidirectional Shift RegistersData can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to indicate the direction.CLKDCQDCQDCQDCQQ0Q1Q2Q3RIGHT/LEFTSerial data inRIGHT.Q0 + RIGHT'.Q2
60. 60Bidirectional Shift Registers4-bit bidirectional shift register with parallel load.CLKI4I3I2I1Serial input for shift-rightDQDQDQDQClear4x1 MUXs1s03 2 1 04x1 MUX3 2 1 04x1 MUX3 2 1 04x1 MUX3 2 1 0A4A3A2A1Serial input for shift-leftParallel inputsParallel outputs
61. 61Bidirectional Shift Registers4-bit bidirectional shift register with parallel load.
62. 62An Application – Serial AdditionMost operations in digital computers are done in parallel. Serial operations are slower but require less equipment.A serial adder is shown below. A A + B.FAxyzSCShift-register AShift-rightCPSIShift-register BSIExternal inputSOSOQDClear
63. 63An Application – Serial AdditionA = 0100; B = 0111. A + B = 1011 is stored in A after 4 clock pulses. Initial: A: 0 1 0 0B: 0 1 1 1Q: 0Step 1: 0 + 1 + 0 S = 1, C = 0 A: 1 0 1 0B: x 0 1 1Q: 0Step 2: 0 + 1 + 0 S = 1, C = 0 A: 1 1 0 1B: x x 0 1Q: 0Step 3: 1 + 1 + 0 S = 0, C = 1 A: 0 1 1 0B: x x x 0Q: 1Step 4: 0 + 0 + 1 S = 1, C = 0 A: 1 0 1 1B: x x x xQ: 0
64. 64Shift Register CountersShift register counter: a shift register with the serial output connected back to the serial input.They are classified as counters because they give a specified sequence of states.Two common types: the Johnson counter and the Ring counter.
65. 65Ring CountersOne flip-flop (stage) for each state in the sequence.The output of the last stage is connected to the D input of the first stage.An n-bit ring counter cycles through n states.No decoding gates are required, as there is an output that corresponds to every state the counter is in.
66. 66Ring CountersExample: A 6-bit (MOD-6) ring counter.CLKQ0DQDQDQDQDQDQQ1Q2Q3Q4Q5CLRPRE100000010000001000000100000010000001
67. 67Johnson CountersThe complement of the output of the last stage is connected back to the D input of the first stage.Also called the twisted-ring counter.Require fewer flip-flops than ring counters but more flip-flops than binary counters.An n-bit Johnson counter cycles through 2n states.Require more decoding circuitry than ring counter but less than binary counters.
68. 68Johnson CountersExample: A 4-bit (MOD-8) Johnson counter.CLKQ0DQDQDQDQQ1Q2Q3'CLRQ'00000001001101111111111011001000
69. 69Johnson CountersDecoding logic for a 4-bit Johnson counter.A'D'State 0ADState 4BC'State 2CD'State 3AB'State 1A'BState 5B'CState 6C'DState 7
70. 70Random Access Memory (RAM)A memory unit stores binary information in groups of bits called words.The data consists of n lines (for n-bit words). Data input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory.The address consists of k lines which specify which word (among the 2k words available) to be selected for reading or writing.The control lines Read and Write (usually combined into a single control line Read/Write) specifies the direction of transfer of the data.
71. 71Random Access Memory (RAM)Block diagram of a memory unit:Memory unit2k wordsn bits per wordk address lineskRead/Writennn data input linesn data output lines
72. 72Random Access Memory (RAM)Content of a 1024 x 16-bit memory:101101011101110110100001100001100010011101110001::111001010101001000111110101011101011000110010101Memory contentdecimal012::102110221023000000000000000000010000000010::111111110111111111101111111111binaryMemory address
73. 73Random Access Memory (RAM)The Write operation:Transfers the address of the desired word to the address linesTransfers the data bits (the word) to be stored in memory to the data input linesActivates the Write control line (set Read/Write to 0)The Read operation:Transfers the address of the desired word to the address linesActivates the Read control line (set Read/Write to 1)
74. 74Random Access Memory (RAM)The Read/Write operation:Two types of RAM: Static and dynamic.Static RAMs use flip-flops as the memory cells.Dynamic RAMs use capacitor charges to represent data. Though simpler in circuitry, they have to be constantly refreshed.
75. 75Random Access Memory (RAM)A single memory cell of the static RAM has the following logic and block diagrams.RSQInputSelectOutputRead/WriteBCOutputInputSelectRead/WriteLogic diagramBlock diagram
76. 76Random Access Memory (RAM)Logic construction of a 4 x 3 RAM (with decoder and OR gates):
77. 77Random Access Memory (RAM)An array of RAM chips: memory chips are combined to form larger memory.A 1K x 8-bit RAM chip:Block diagram of a 1K x 8 RAM chipRAM 1K x 8DATA (8)ADRS (10)CSRWInput dataAddressChip selectRead/write(8)Output data8810
78. 78Random Access Memory (RAM)4K x 8 RAM.1K x 8DATA (8)ADRS (10)CSRWRead/write(8)Output data1K x 8DATA (8)ADRS (10)CSRW(8)1K x 8DATA (8)ADRS (10)CSRW(8)1K x 8DATA (8)ADRS (10)CSRW(8)0–10231024 – 20472048 – 30713072 – 4095Input data8 lines01232x4 decoderLinesLines0 – 911 10S0S1Address
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