APPLICATION NOTE U UC Controlled Power Factor Correction Circuit Design PHILIP C - PDF document

APPLICATION NOTEU-134 UC3854 Controlled Power Factor Correction Circuit Design PHILIP C. TODDABSTRACTThis Application Note describes the concepts and design of a boost preregulator for power factor correc- tion. This note covers the important specifications for power factor correction, the boost power circuit de-sign and the UC3854 integrated circuit which controls the converter. A complete design procedure is given supersedes Application Note U- 125 "Power Factor Correction With the UC3854. ” INTRODUCTION The objective of active power factor correction is tomake the input to a power supply look like a simpleresistor. An active power factor corrector does thisby programming the input current in response to and either one will degrade the power factor. The most general definition of power factor is the ratio of real power to apparent power. Where P is the real input power and Vrms and Irmsare the root mean square (RMS) voltage and cur- power and the product of the RMS voltage and cur- rent will be the same and the power factor will be1.0. If the load is not a pure resistance the power factor will be below 1.0. Phase displacement is a measure of the reactanceof the input impedance of the active power factorcorrector. Any amount of reactance, either induc-tive or capacitive will cause phase displacement ofthe input current waveform with respect to the input between the voltage and current sinusoids. PF=Cose The amount of displacement between the voltageand current indicates the degree to which the loadis reactive. If the reactance is a small part of theimpedance the phase displacement will be small.An active power factor corrector will generatephase displacement of the input current if there isphase shift in the feedforward signals or in the con-trol loops. Any filtering of the AC line current will also produce phase displacement. 3-269 APPLICATION NOTEU-134 Power Factor Versus DistortionPower Factor Versus Distortion Table 1 several sources: the feedforward signals, the feed- 0.90. The trend among the world standards organiza-tions responsible for power quality is to specifymaximum limits for the amount of current allowedat each of the harmonics of the line frequency. IEC555-2 specifies each harmonic up through and be-yond the 15th and the amount of current permissi-ble at each. Table 1 lists the requirements for IEC555-2 as of the time of this writing. There are twoparts to the specification, a relative distortion and 3-270 APPLICATION NOTEU-134 Figure 1 Basic Configuration of High Power FactorControl Circuitpeak current mode control or average currentconcept. An amplifier is used in the feedback loopmode control may be used. Both techniques mayaround the boost power stage so that input currentbe implemented with the UC3854. Peak currenttracks the programming signal with very little error.mode control has a low gain, wide bandwidth cur-This is the advantage of average current moderent loop which generally makes it unsuitable for acontrol and it is what makes active power factorhigh performance power factor corrector sincecorrection possible. Average current mode controlthere is a significant error between the program-is relatively easy to implement and is the methodming signal and the current. This will produce dis- described here.tortion and a poor power factor. A block diagram of a boost power factor correctorAverage current mode control is based on a simplecircuit is shown in Figure 1. The power circuit of a Figure 2. Preregulator Waveforms 3-271 APPLICATION NOTEU-134 boost power factor corrector is the same as that ofa dc to dc boost converter. There is a diode bridgeahead of the inductor to rectify the AC input volt-age but the large input capacitor which would nor-mally be associated with the AC to DC conversionfunction has been moved to the output of the boostconverter. If a capacitor follows the input diodebridge it is a small one used only for noise control.The output of the boost regulator is a constant volt-age but the input current is programmed by the in-put voltage to be a half sine wave. The power flowControl CircuitsAn active power factor corrector must control boththe input current and the output voltage. The cur-rent loop is programmed by the rectified line volt-age so that the input to the converter will appear tobe resistive. The output voltage is controlled bychanging the average amplitude of the current pro-gramming signal. An analog multiplier creates thecurrent programming signal by multiplying the rec-tified line voltage with the output of the voltage er- Figure 3. High Power Factor into the output capacitor is not constant but is asine wave at twice the line frequency since poweris the instantaneous product of voltage an current.This is shown in Figure 2. The top waveformshows the voltage and the current into the powerfactor corrector and the second waveform showsthe flow of energy into and out of the output ca-pacitor. The output capacitor stores energy whenthe input voltage is high and releases the energywhen the input voltage is low to maintain the out-put power flow. The third waveform in Figure 2shows the charging and discharging current. Thiscurrent has a different shape from the input currentand is almost entirely at the second harmonic ofthe AC line voltage. This flow of energy into andout of the capacitor results in ripple voltage at thesecond harmonic also and this is shown in thefourth waveform in Figure 2. Note that the voltageripple is displaced by 90 degrees relative to thecurrent since this is reactive energy storage. Theoutput capacitor must be rated to handle the sec-ond harmonic ripple current as well as the high fre-quency ripple current from the boost converterswitch which modulates it.ror amplifier so that the current programming sig-nal has the shape of the input voltage and an aver-age amplitude which controls the output voltage.Figure 3 is a block diagram which shows the basiccontrol circuit arrangement necessary for an activepower factor corrector. The output of the multiplieris the current programming signal and is called Imofor multiplier output current. The multiplier inputfrom the rectified line voltage is shown as a currentin Figure 3 rather than as a voltage signal becausethis is the way it is done in the UC3854.Figure 3 shows a squarer and a divider as well asa multiplier in the voltage loop. The output of thevoltage error amplifier is divided by the square ofthe average input voltage before it is multiplied bythe rectified input voltage signal. This extra cir-cuitry keeps the gain of the voltage loop constant,without it the gain of the voltage loop would changeas the square of the average input voltage. The av-erage value of the input voltage is called the feed-forward voltage or Vff since it provides an openloop correction which is fed forward into the volt-age loop. It is squared and then divided into thevoltage error amplifier output voltage (Vvea). 3-272 APPLICATION NOTEU-134 The current programming signal must match therectified line voltage as closely as possible to maxi-mize the power factor. If the voltage loop band-width were large it would modulate the inputcurrent to keep the output voltage constant andthis would distort the input current horribly. There-fore the voltage loop bandwidth must be less thanthe input line frequency. But the output voltagetransient response must be fast so the voltage loopbandwidth must be made as large as possible. Thesquarer and divider circuits keep the loop gain con-stant so the bandwidth can be as close as possible rent and is displaced by 90 degrees. put. Needless to say, the feedforward ripple voltagemust be kept small to achieve a low distortion inputcurrent. The ripple voltage could be made smallwith a single pole filter with a very low cutoff fre-quency. However, fast response to changes of theinput voltage is also desirable so the responsetime of the filter must be fast. These two require-ments are, of course, in conflict and a compromisemust be found. A two pole filter on the feedforwardinput has a faster transient response than a single 3-273 APPLICATION NOTEU-134 phase with the input current. The third harmonicvoltage loop stable. If the phase margin is reducedcomponent of the input current resulting from the input voltage. feedforward voltage the line current waveform willcontain 3% third harmonic distortion.The output voltage has ripple at the second har-monic due to the ripple current flowing through theoutput capacitor. This ripple voltage is fed backthrough the voltage error amplifier to the multiplierand, like the feedforward voltage, programs the in- sponse and low input current distortion.voltage. Figure 4. Cusp Distortion The voltage loop of a boost converter with averagecurrent mode control has a control to output trans-fer function which has a single pole roll off charac-teristic so it could be compensated with a flat gain gives the greatest bandwidth and provides a 45 de-gree phase margin. Cusp DistortionCusp distortion occurs just after the AC line inputhas crossed zero volts. At this point the amount ofcurrent which is required by the programming sig-nal exceeds the available current slew rate. Whenthe input voltage is near zero there is very littlevoltage across the inductor when the switch isclosed so the current cannot ramp up very quicklyso the available slew rate is too low and the inputcurrent will lag behind the desired value for a shortperiod of time. Once the input current matches the quency. APPLICATION NOTEU-134 UC3854 Block Diagram A block diagram of the UC3854 is shown in Figure5 and is the same as the one in the device datasheet. This integrated circuit contains the circuitsnecessary to control a power factor corrector. TheUC3854 is designed to implement average currentmode control but is flexible enough to be used for awide variety of power topologies and control meth- ods. The top left corner of Figure 5 contains the undervoltage lock out comparator and the enable com-parator. The output of both of these comparatorsmust be true to allow the device to operate. The in-verting input to the voltage error amplifier is con-nected to pin 11 and is called Vsens. The diodesshown around the voltage error amplifier are in-tended to represent the functioning of the internalcircuits rather than to show the actual devices. Thediodes shown in the block diagram are ideal di-odes and indicate that the non-inverting input tothe error amplifier is connected to the 7.5Vdc refer-ence voltage under normal operation but is alsoused for the slow start function. This configurationlets the voltage control loop begin operation beforethe output voltage has reached its operating pointand eliminates the turn-on overshoot whichplagues many power supplies. The diode shownbetween pin 11 and the inverting input of the erroramplifier is also an ideal diode and is shown toeliminate confusion about whether there might bean extra diode drop added to the reference or not.In the actual device we do it with differential ampli-fiers. An internal current source is also provided forcharging the slow start timing capacitor.input to the multiplier. The other input to the multi-plier is pin 6, lac, and this is the input for the pro-gramming wave shape from the input rectifiers.This pin is held at 6.0 volts and is a current input.The feedforward input, Vff, is pin 8 and its value issquared before being fed into the divider input ofthe multiplier. The lset current from pin 12 is alsoused in the multiplier to limit the maximum outputcurrent. The output current of the multiplier is Imoand it flows out of pin 5 which is also connected tothe non-inverting input of the current error ampli- fier. The inverting input of the current amplifier is con-nected to pin 4, the lsens pin. The output of thecurrent error amplifier connects to the pulse widthmodulation (PWM) comparator where it is com-pared to the oscillator ramp on pin 14. The oscilla-tor and the comparator drive the set-reset flip-flopwhich, in turn, drives the high current output on pin16. The output voltage is clamped internally to theUC3854 at 15 volts so that power MOSFETs willnot have their gates over driven. An emergencypeak current limit is provided on pin 2 and it willshut the output pulse off when it is pulled slightlybelow ground. The reference voltage output is con-nected to pin 9 and the input voltage is connected to pin 15.DESIGN PROCESSPower Stage Design The output of the voltage error amplifier, Vvea, isavailable on pin 7 of the UC3854 and it is also anThis analysis of the power stage design makes useof a 250W boost converter as an example. Thecontrol circuit for a boost power factor correctordoes not change much with the power level of theconverter. A 5000 watt power factor corrector willhave almost the same control circuits as a 50 watt Figure 5. UC3854 Block Diagram 3-275 APPLICATION NOTEU-134 Figure 6.Complete Schematic of 250W Power Factor Preregulator 3-276 APPLICATION NOTEU-134 corrector. The power stage will be different but thedesign process will remain the same for all powerfactor corrector circuits. Since the design processis the same and the power stage is scalable a 250watt corrector serves well as an example and itcan be readily scaled to higher or lower output lev-els. Figure 6 is the schematic diagram of the cir-cuit. Please refer to this schematic in the discussion of the design process which follows. SpecificationsThe design process starts with the specificationsfor the converter performance. The minimum andmaximum line voltage, the maximum output power,and the input line frequency range must be speci-fied. For the example circuit the specifications are:Maximum power output: 250W Input voltage range: 80-27OVacLine frequency range: 47-65Hz This defines a power supply which will operate al-most anywhere in the world. The output voltage ofa boost regulator must be greater than the peak ofthe maximum input voltage and a value 5% to 10%higher than the maximum input voltage is recom-mended so the output voltage is chosen to be 400Vdc. Switching FrequencyThe choice of switching frequency is generallysomewhat arbitrary. The switching frequency mustbe high enough to make the power circuits smalland minimize the distortion and must be lowenough to keep the efficiency high. In most appli-cations a switching frequency in the range of20KHz to 300KHz proves to be an acceptablecompromise.The example converter uses aswitching frequency of I00KHz as a compromisebetween size and efficiency. The value of the in-ductor will be reasonably small and cusp distortionwill be minimized, the inductor will be physicallysmall and the loss due to the output diode will notbe excessive. Converters operating at higherpower levels may find that a lower switching fre-quency is desirable to minimize the power losses.Turn-on snubbers for the switch will reduce theswitching losses and can be very effective in allow-ing a converter to operate at high switching fre- quency with very high efficiency. Inductor SelectionThe inductor determines the amount of high fre-quency ripple current in the input and its value ischosen to give some specific value of ripple cur-rent. Inductor value selection begins with the peak PFC CURRENTS VS INPUT VOLTAGE VIN (AC) VOLTS Figure 7 3-277 APPLICATION NOTEU-134 current of the input sinusoid. The maximum peakcurrent occurs at the peak of the minimum line voltage and is given by: For the example converter the maximum peak line current is 4.42 amps at a Vin of 80Vac. The maximum ripple current in a boost converteroccurs when the duty factor is 50% which is alsowhen the boost ratio M=Vo/Vin=2. The peak valueof inductor current generally does not occur at thispoint since the peak value is determined by thepeak value of the programmed sinusoid. The peakvalue of inductor ripple current is important for cal-culating the required attenuation of the input filter.Figure 7 is a graph of the peak to peak ripple cur-rent in the inductor versus input voltage for the ex- ample converter. The peak-to-peak ripple current in the inductor isnormally chosen to be about 20% of the maximum sary are given below: Where Al is the peak-to-peak ripple current. In theexample 250W converter D=0.71, Al=900ma, andL=0.89mH. For convenience the value of L is rounded up to 1.0mH. The high frequency ripple current is added to theline current peak so the peak inductor current isthe sum of peak line current and half of the peak-to-peak high frequency ripple current. The inductormust be designed to handle this current level. Forour example the peak inductor current is 5.0 amps.The peak current limit will be set about 10% higherat 5.5 amps.Output CapacitorThe factors involved in the selection of the outputcapacitor are the switching frequency ripple cur-rent, the second harmonic ripple current, the DCoutput voltage, the output ripple voltage and thehold-up time. The total current through the outputcapacitor is the RMS value of the switching fre-quency ripple current and the second harmonic ofthe line current. The large electrolytic capacitorswhich are normally chosen for the output capacitorhave an equivalent series resistance whichchanges with frequency and is generally high at necessary ESR and temperature rise information. The hold-up time of the output often dominates anyother consideration in output capacitor selection.Hold-up is the length of time that the output voltageremains within a specified range after input powerhas been turned off. Hold-up times of 15 to 50 milli-seconds are typical. In off-line power supplies witha 400Vdc output the hold-up requirement generallyworks out to between 1 and 2pF per watt of output.In our 250W example the output capacitor is 450pF. If hold-up is not required the capacitor willbe much smaller, perhaps 0.2pF per watt, and thenripple current and ripple voltage are the major con- cern. Hold-up time is a function of the amount of energystored in the output capacitor, the load power, out-put voltage and the minimum voltage the load willoperate at. This can be expressed in an equation to define the capacitance value in terms of the hold-up time. Where Co is the output capacitor, Pout is the loadpower, At is the hold-up time, Vo is the output volt-age and Vo(min) is the minimum voltage the loadwill operate at. For the example converter Pout is250W, is 64msec, Vo is 400V and Vo(min) is300V so Co is 45OuF. Switch and DiodeThe switch and diode must have ratings which aresufficient to insure reliable operation. The choice ofthese components is beyond the scope of this Ap-plication Note. The switch must have a current rat-ing at least equal to the maximum peak current in 3-278 APPLICATION NOTE UC3854 Figure 8.Current Transformers Used with Negative Output UC3854 Figure 9. Current Transformers Used with Positive Output I APPLICATION NOTEU-134 the inductor and a voltage rating at least equal tothe output voltage. The same is true for the outputdiode. The output diode must also be very fast toreduce the switch turn-on power dissipation and tokeep its own losses low. The switch and diodemust have some level of derating and this will vary depending on the application. For the example circuit the diode is a high speed,high voltage type with 35ns reverse recovery,600Vdc breakdown, and 8A forward current rat-ings. The power MOSFET in the example circuithas a 500Vdc breakdown and 23Adc current rat- slower diode. Current SensingThere are two general methods for current sens-ing, a sense resistor in the ground return of the rent. The configuration of the multiplier output and thecurrent error amplifier are different depending onwhether a resistor is used for current sensing orwhether current transformers with positive output loop. The resistor current sense configuration is used inthe example converter (Figure 6) so the invertinginput to the current error amplifier (pin 4) is con- through Rci to ground. The voltage across Rs, the current sense resistorin the example converter, goes negative with re-spect to ground so it is important to be sure thatthe pins of the UC3854 do not go below ground.The voltage across the sense resistor should bekept small and pins 2 and 5 should be clamped toprevent their going negative. A peak value of 1 voltor so across the sense resistor provides a signallarge enough to have good noise margin but whichis small enough to have low power dissipation. 3-280 APPLICATION NOTEU-13 The equation for the voltage divider is given below:the average value of a half sine will be 243Vdc and the peak will be 382V. The Vff voltage divider has two DC conditions toWhere Rpk1 and Rpk2 are the resistors of the volt-age divider, Vref is 7.5 volts on the UC3854, andVrs is the voltage across the sense resistor Rs atthe current limit point. The current through Rpk2should be around 1 mA. The peak current limit inthe example circuit is set at 5.4 amps with an Rpk1 current limit slightly. Multiplier Set-upThe multiplier/divider is the heart of the power fac-tor corrector. The output of the multiplier programsthe current loop to control the input current to givea high power factor. The output of the multiplier istherefore a signal which represents the input line current. Unlike most design tasks where the design beginsat the output and proceeds to the input the designof the multiplier circuits must begin with the inputs. voltage. Feedforward VoltageVff is the input to the squaring circuit and theUC3854 squaring circuit generally operates with a current waveform. The example circuit uses the UC3854 so the maxi-mum value of Vff is 4.5 volts. If Rff1, the top resis-tor of the divider, is 910K and Rff2, the middleresistor, is 91 K and Rff3, the bottom resistor, is20K the maximum value of Vff will be 4.76 voltswhen the input voltage is 270Vac RMS and the DCaverage value will be 243 volts. When the input is 12% higher. The clamp on the output of the voltage error ampli-fier is what sets the minimum value of Vff at 1.414volts. This can be seen by plugging these valuesinto the equation for the multiplier output currentgiven above. When Vff is large the inherent errorsof the multiplier are magnified because Vvea/Vffbecomes small. If the application has a wide inputvoltage range and if a very low harmonic distortion 3-281 APPLICATION NOTEU-134 is required then Vff may be changed to the rangeof 0.7 to 3.5 volts. To do this an external clampMUST be added to the voltage error amplifier tohold its output below 2.00 volts. In general, how- ever, this is not a recommended practice. Multiplier Input CurrentThe operating current for the multiplier comes fromthe input voltage through Rvac. The multiplier hasthe best linearity at relatively high currents, but therecommended maximum current is 0.6mA. At highline the peak voltage for the example circuit is382Vdc and the voltage on pin 6 of the UC3854 is 150K for Rb1 will provide the correct bias. The maximum output of the multiplier occurs at thepeak of the input sine wave at low line. The maxi-mum output current from the multiplier can be cal-culated from the equation for Imo, given above, forthis condition. The peak value of lac will be 182 mi-croamps when Vin is at low line. Vvea will be 5.0volts and Vff will be 2.0. Imo will then be 365 mi-croamps maximum. Imo may not be greater than accordingly. The lset current places another limitation on themultiplier output current. Imo may not be largerthan 3.75 / Rset. For the example circuit this givesRset = 10.27K maximum so a value of 10K is cho- sen. The current out of the multiplier, Imo, must besummed with a current proportional to the inductorcurrent to close the voltage feedback loop. Rmo, aresistor from the output of the multiplier to the cur-rent sense resistor, performs the function and themultiplier output pin becomes the summing junc-tion. The average voltage on pin 5 will be zero un-der normal operation but there will be switching mined from: Where Ct is the value of the timing capacitor and fsis the switching frequency in Hertz. For the exam- 0.00125pF. Current Error Amplifier CompensationThe current loop must be compensated for stableoperation. The boost converter control to input cur-rent transfer function has a single pole response athigh frequencies which is due to the impedance ofthe boost inductor and the sense resistor (Rs)forming a low pass filter. The equation for the con-trol to input current transfer function is:Where Vrs is the voltage across the input currentsense resistor and Vcea is the output of the currenterror amplifier. Vout is the DC output voltage, Vs isthe peak-to-peak amplitude of the oscillator ramp,sL is the impedance of the boost inductor (alsojwL), and Rs is the sense resistor (with a current 3-282 APPLICATION NOTEU-134 with the slope VoRs/L (with current sense trans-gives a pole at 128KHz. This is actually above theformers it will be VoRs/NL). This slope, multipliedswitching frequency so a larger value of capacitorby the gain of the current error amplifier at thecould have been used but 62pF is adequate in thisswitching frequency, must be equal to the slope of case. the oscillator ramp (also in volts per second) forproper compensation of the current loop. If the gainVoltage Error Amplifier Compensation voltage increases. The loop crossover frequency can be found fromthe above equation if the gain of the current erroramplifier is multiplied with it and it is set equal toone. Then rearrange the equation and solve for the crossover frequency. The equation becomes: Where fci is the current loop crossover frequencyand Rcz/Rci is the gain of the current error ampli-fier. This procedure will give the best possible re- sponse for the current loop. In the example converter the output voltage is current loop crossover frequency is 15.9KHz. The placement of the zero in the current error am- (271 x fci xRcz). The example converter has Rcz=20K andfci=l5.9KHz so Ccz=500pF. A value of 620pF waschosen to give a little more phase margin.A pole is normally added to the current error ampli-fier response near the switching frequency to re-duce noise sensitivity. If the pole is above half theswitching frequency the pole will not affect the fre-quency response of the control loop. The exampleconverter uses a 62pF capacitor for Ccp whichThe voltage control loop must be compensated forstability but because the bandwidth of the voltageloop is so small compared to the switching fre-quency the requirements for the voltage control keep the power factor high. The basic low frequency model of the output stageis a current source driving a capacitor. The powerstage and the current feedback loop compose thecurrent source and the capacitor is the output ca-pacitor. This forms an integrator and it has a gaincharacteristic which rolls off at a constant 20dB per quency response. given by: Where Vopk is the peak value of the output ripplevoltage (the peak to peak value will be twice this),fr is the ripple frequency which is the second har-monic of the input line frequency, Co is the value ofthe output capacitance and Vo is the DC outputvoltage. The example converter has a peak ripple voltage of 1.84Vpk. The amount of distortion which the ripple contrib-utes to the input must be decided next. This deci- 3-283 APPLICATION NOTEU-134 sion is based on the specification for the converter.The example converter is specified for 3% THD so0.75% THD is allocated to this component. Thismeans that the ripple voltage at the output of thevoltage error amplifier is limited to 1.5%. The volt-age error amplifier has an effective output range (AVvea) of 1.0 to 5.0 volts so the peak ripple volt-age at the output of the voltage error amplifier isgive by Vvea(pk) = %Ripple x AVvea. The exampleconverter has a peak ripple voltage at the output ofthe voltage error amplifier of 60mVpk.The gain of the voltage error amplifier, Gva, at thesecond harmonic ripple frequency is the ratio of thetwo values given above. The peak ripple voltageallowed on the output of the voltage error amplifieris divided by the peak ripple voltage on the outputcapacitor. For the example converter Gva is 0.0326.dissipation of about 300mW. Cvf, the feedback capacitor sets the gain at thesecond harmonic ripple frequency and is chosen togive the voltage error amplifier the correct gain atthe second harmonic of the line frequency. The equation is simply: The criteria for the choice of Rvi, the next step inthe design process, are reasonably vague. Thevalue must be low enough so that the opamp biascurrents will not have a large effect on the outputand it must be high enough so that the power dissi-pation is small. In the example converter a 511 Kresistor was chosen for Rvi and it will have powerlumped into the power stage gain and their effect isto transform the output of the voltage error ampli-fier into a power control signal as was noted ear-lier. This allows us to express the transfer functionof the boost stage simply in terms of power. The equation is: Where Gbst is the gain of the boost stage includingthe multiplier, divider and squarer, Pin is the aver-age input power, Xco is the impedance of the out-put capacitor, AVvea is the range of the voltageerror amplifier output voltage (4 volts on the UC3854) and Vo is the DC output voltage. The gain of the error amplifier above the pole in its frequency response is given by: Where Gva is the gain of the voltage error ampli-fier, Xcf is the impedance of the feedback capaci-tance and Rvi is the input resistance.The gain of the total voltage loop is the product ofGbst and Gva and is given by the this equation:Note that there are two terms which are dependenton f, Xco and Xcf. This function has a second or-der slope (-40dB per decade) so it must be a func-tion of frequency squared. To solve for the unitygain frequency set Gv equal to one and rearrangethe equation to solve for fvi. Xco is replaced withThe example converter has a Cvf value of 0.08uF. and Xcf is replaced with 1/(2&M). If this value is rounded down to Cvf=O.O47pF the The equation becomes: phase margin will be a little better with only a little more distortion so this value was chosen. The output voltage is set by the voltage divider Rviand Rvd. The value of Rvi is already determinedso Rvd is found from the desired output voltageand the reference voltage which is 7.50Vdc. In theexample Rvd=l0K will give an output voltage of390Vdc. This could be trimmed up to 400VDC witha 414K resistor in parallel with Rvd but for this ap-plication 390Vdc is acceptable. Rvd has no effecton the AC performance of the active power factorcorrector. Its only effect is to set the DC output volt- age. The frequency of the pole in the voltage error am-plifier can be found from setting the gain of theloop equation equal to one and solving for the fre-quency. The voltage loop gain is the product of theerror amplifier gain and the boost stage gain, whichcan be expressed in terms of the input power. Themultiplier, divider and squarer terms can all beSolving for fvi in the example converter givesfvi=19.14Hz. The value of Rvf can now be found bysetting it equal to the impedance of Cvf at fvi. The equation is: Rvf=1 l(27rfviCvf). In the example converter a value of 177K is calcu- lated and 174K is used. Feedforward Voltage Divider Filter CapacitorsThe percentage of second harmonic ripple voltageon the feedforward input to the multiplier results inthe same percentage of third harmonic ripple cur-rent on the AC line. The capacitors in the feedfor-ward voltage divider (Cff1 and Cff2) attenuate theripple voltage from the rectified input voltage. The 3-284 APPLICATION NOTEU-134 second harmonic ripple is 66.2% of the input ACline voltage. The amount of attenuation required, orthe “gain” of the filter, is simply the amount of thirdharmonic distortion allocated to this distortionsource divided by 66.2% which is the input to thedivider. The example circuit has an allocation of1.5% total harmonic distortion from this input sothe required attenuation is Gff = 1.5 / 66.2 = 0.0227. The recommended divider string impliments a sec-ond order filter because this gives a much fasterresponse to changes in the RMS line voltage. Typi-cally, it is about six times faster. The two poles ofthe filter are placed at the same frequency for thewidest bandwidth. The total gain of the filter is the quency or: The example converter has a filter gain of 0.0227and a section gain of 0.15 and a ripple frequencyof120Hz so the cutoff frequency is fc=0.15x120=18Hz. The cutoff frequency is used to calculate the val-ues for the filter capacitors since, in this appliva-tion, the impedance of the capacitor will equal theimpedance of the load resistance at the cutoff fre-quency. The two equations given below are usedto calculate the two capacitor values. 20K; so, This completes the design of the major circuits of an active power factor corrector.DESIGN PROCEDURE SUMMARY This section contains a brief, step-by-step sum-mary of the design procedure for an active powerfactor corrector. The example circuit used above is repeated here. 1. Specifications: Determine the operating require- ments for the active power factor corrector.Example: Pout (max): 250W Vin range: 80-270VacLine frequency range: 47-65Hz Output voltage: 400Vdc Select switching frequency:Example:Inductor selection: Example:Ipk=1.41 x250/80=4.42 ampsB. Ripple current. AI = 0.2 x Ipk Example: = 0.2x4.42 = 0.9 amps peak to peak C. Determine the duty factor at Ipk whereVin(peak) is the peak of the rectified line volt- age at low line.Example: D. Calculate the inductance. fs is the switching frequency.Round up to 1.0mH. 4. Select output capacitor. With hold-up time, use the equation below. Typical values for Co are 1 yF to 2uF per watt. If hold-up is not requireduse the second harmonic ripple voltage and to- tal capacitor power dissipation to determineminimum size of the capacitor. At is the hold-uptime in seconds and V1 is the minimum output 3-285 APPLICATION NOTEU-134 capacitor voltage.Example: Select current sensing resistor. If current trans- is a typical value for Vrs.Example: lpk(max)=4.42+0.45 = 5.0amps peak B. Calculate sense resistor value. Rs =Vrs C. Calculate the actual peak sense voltage. Vrs(pk)=lpk(max)xRs 6. Set independent peak current limit. Rpk1 and Rpk2 are the resistors in the voltage divider.Choose a peak current overload value,Ipk(ovld). A typical value for Rpk1 is 10K. Vrs ( ovld ) = Ipk ( olvd ) x Rs Example: Rpk2 =Vrs ( ovld ) x Rpk1Vref multiplier output current, Km=1 , lac is the multi- plier input current, Vff is the feedforward volt-age and Vvea is the output of the voltage error amplifier. vff 2 A. Feedforward voltage divider. Change Vinfrom RMS voltage to average voltage of therectified input voltage. At Vin(min) the voltageat Vff should be 1.414 volts and the voltage at Vin ( av ) = Vin ( min ) x 0.9 The following two equations are used to findthe values for the Vff divider string. A value of 1 Megohm is usually chosen for the divider in- put impedance. The two equations must besolved together to get the resistor values. vff = 1.414v= Vin ( av ) x Rff3Rff1 + Rff2 + Rff3Vnode = 7.5V = Vin(av)x(Rff2+Rff3) Rff1 + Rff2 + Rff3 Example: Rff1=910K, Rff2=91K, and Rff3=20KB. Rvac selection. Find the maximum peak line voltage. Divide by 600 microamps, the maximum mul-tiplier input current. Rvac = Vpk(max) Rvac=(382)/6E-4=637K. Choose 620K C. Rb1 selection. This is the bias resistor. Treatthis as a voltage divider with Vref and Rvacand then solve for Rb1. The equation be- comes: Rb1 = 0.25 Rvac Example:Rb1=0.25Rvac=155K. Choose 150K D. Rset selection. Imo cannot be greater thantwice the current through Rset. Find the multi-plier input current, lac, with Vin(min). Thencalculate the value for Rset based on thevalue of lac just calculated. Rset = 3.75 2 x lac ( min ) Example: APPLICATION NOTE U-134 Choose 10 Kohms E. Rmo selection. The voltage across Rmomust be equal to the voltage across Rs at thepeak current limit at low line input voltage. Rmo = Vrs ( pk) x 1.12 2 x lac(min) =15.7KHz D. Ccz selection. Choose a 45 degree phase quency.Example: Choose 3.9Kohms 8. Oscillator frequency. Calculate Ct to give the de- sired switching frequency.Choose 620pF E. Ccp selection. The pole must be above fs/2.Ct= 1.25 Rset x fs Example:Ct=1.25/(10K x 100K)=1.25nF. 9. Current error amplifier compensation.A. Amplifier gain at the switching frequency. Calculate the voltage across the sense resistor due to the inductor current downslope andthen divide by the switching frequency. Withcurrent transformers substitute (Rs/N) for Rs. The equation is:Example: 100Kx20K)=80pf. Choose 62pF 10. Harmonic distortion budget. Decide on a maxi-mum THD level. Allocate THD sources as nec- essary. The predominant AC line harmonic isthird. Output voltage ripple contributes 1/2% third harmonic to the input current for each 1%ripple at the second harmonic on the output ofthe error amplifier. The feedforward voltage,Vff, contributes 1% third harmonic to the inputcurrent for each 1% second harmonic at the Vff input to the UC3854.Example: as the specification. 1.5% is allocated to the3% third harmonic AC input current is chosen AVrs =(400x0.25)/(0.001 x100,000)=1.0Vpk This voltage must equal the peak to peak am-plitude of Vs, the voltage on the timing capaci-tor (5.2 volts). The gain of the error amplifier is therefore given by: Vff input and 0.75% is allocated to the outputripple voltage or 1.5% to Vvao. The remain-ing 0.75% is allocated to miscellaneous non- linearities. 11. Voltage error amplifier compensation. A. Output ripple voltage. The output ripple isgiven by the following equation where fr is the second harmonic ripple frequency: B. Feedback resistors. Set Rci equal to Rmo. Rci = RmoRcz = Gca x Rci B. Amplifier output ripple voltage and gain.Vo(pk) must be reduced to the ripple voltage C. Current loop crossover frequency. allowed at the output of the voltage error am-plifier. This sets the gain of the voltage erroramplifier at the second harmonic frequency. The equation is:Example: APPLICATION NOTEU-134 For the UC3854 Vvao is 5-1=4VExample: C. Feedback network values. Find the compo-nent values to set the gain of the voltage erroramplifier. The value of Rvi is reasonably arbi- trary. Choose Rvi=511KExample: Choose 0.047p D. Set DC output voltage.Example: Choose 10.0KE. Find pole frequency. fvi = unity gain fre- quency of voltage loop.Example:19.1 HzF. Find Rvf.Example: x47E-9)=177K. Choose 174K12. Feedforward voltage divider capacitors. These capacitors determine the contribution of Vff tothe third harmonic distortion on the AC inputcurrent. Determine the amount of attenuationneeded. The second harmonic content of therectified line voltage is 66.2%. %THD is the al- lowed percentage of harmonic distortion budg- eted to this input from step 10 above. %THD Gff = 66.2% Example: Use two equal cascaded poles. Find the polefrequencies. fr is the second harmonic ripple frequency. Select Cff1 and Cff2.Example: L. H. Dixon, “High Power Factor Preregulator forOff -Line Supplies,” Unitrode Power Supply DesignSeminar Manual SEM600, 1988 (Reprinted in sub-sequent editions of the Manual.)L. H. Dixon, “High Power Factor Switching Pre-regulator Design Optimization,” Unitrode PowerSupply Design Seminar Manual SEM700, 1990(Reprinted in subsequent editions of the Manual.)L. H. Dixon, “Average Current Mode Control ofSwitching Power Supplies,” Unitrode Power SupplyDesign Seminar Manual SEM700,1990 (Reprinted in subsequent editions of the Manual.) S. Freeland, “Input-Current Shaping for Single-Phase A C C Power Converters,” Ph.D. Thesis, California Institute of Technology, 1988 UNITRODE CORPORATION7 CONTINENTAL BLVD l MERRIMACK, NH 03054TEL. (603) 424-2410 l FAX (603) 424-3460 3-288 IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgement, including thosepertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI's standard warranty. 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