Sequential Circuits 1 Logic Circuits Review 2 Logic Circuits Sequential Circuits Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs ID: 673551
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Slide1
5 Chapter
Synchronous Sequential Circuits
1Slide2
Logic Circuits- Review
2
Logic Circuits
Sequential Circuits
Combinational Circuits
Consists of logic gates whose outputs are determined from the current combination of inputs.
Performs an operation that can be specified by a set of Boolean functions.
Employ storage elements in addition to logic gates.
Outputs are a function of the inputs and the state of the storage elements.
Output depend on present value of input + past input.Slide3
OverviewStorage Elements and Analysis
Introduction to sequential circuitsTypes of sequential circuitsStorage elementsLatches
Flip-flops
Sequential circuit analysis
State tables
State
diagrams3Slide4
5.2 Sequential Circuits
A Sequential circuit contains:
Storage
elements :
Latches or Flip-Flops
Combinatorial Logic:
Implements a multiple-output switching functionInputs are signals from the
outside.
Outputs are signals to the outside.
Other inputs, State or Present State, are signals from storage elements.
The
remaining outputs
,
Next State
are inputs to storage elements.
4
Combinational
Logic
Storage Elements
Inputs
Outputs
State
Next
StateSlide5
Sequential Logic
Output function
Outputs = g(Inputs, State
)
Next state function
Next State = f(Inputs, State)
5
Combina-tional
Logic
Storage Elements
Inputs
Outputs
State
Next
State
5.2 Sequential CircuitsSlide6
Types of Sequential Circuits
Depends on the
time
s
at which:
storage elements observe their inputs, and
storage elements change their state
SynchronousBehavior defined from knowledge of its signals
at
discrete instances of time
Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a
clock
)
Asynchronous
Behavior defined from knowledge of inputs
at
any
instant of time
and the order in continuous time in which inputs change
If clock just regarded as another input, all circuits are asynchronous!
6
5.2 Sequential CircuitsSlide7
5.3 Storage Elements :Latches
Storage elementsMaintain a binary state (0 or 1) indefinitely as long as power is delivered to the circuit
Switch states (0
1 or 10
) when directed by an input signal
The major difference among
storage elements are in the number of inputs they possess and in the manner in which the inputs affect the binary state.Most basic storage elementUsed mainly to construct Flip-FlopsAsynchronous storage circuit
Types of latches:SR LatchesD Latches7
X = XSlide8
Basic (NOR) S –
R Latch
Cross-coupling
two
NOR
gates gives theS – R Latch:8
S (set)
R (reset)
Q
Q
Graphic Symbol
R
S
Q
Q
5.3 Storage Elements :Latches
Function diagramSlide9
Basic (NOR) S –
R Latch
9
Q’
t+1
Q
t+1
QR
S1
Q t+1=Q =0
00001
1
0
0
1
0
0
1
0
10
1100
1
001
0110
1؟Undefined
0
11
؟undefined11
1
Q
t+1R
SQ
t+1=Q No change
00
Reset to 01
0Set to 1
01undefined1
1
Qnext
=(R+Q’ current)’Q’next=(S+Qcurrent)’
5.3 Storage Elements :Latches
Function tableSlide10
Both Qnext and
Q’next would become
0
,which contradicts
the assumption that Q and Q’ are always complemented.
Another
problem is what happen if we then make S=0 and R=0 together:Qnext
= (0+0)’=1Q’next =(0+0)’=1But
these new values go back into the NOR gates and we then get Q=Q’=0 againQnext
= (1+1)’=0Q’next
=(1+1)’=0So the circuit enters an infinite loop , where Q and Q’ cycle between 0 and 1 forever.10
5.3 Storage Elements :Latches
What about SR=11?Slide11
Clocked S - R Latch
Adding two NANDgates to the basic
Ś
-
Ŕ
NAND latch
gives the clockedS – R latch:
Has a time sequence behavior similar to the basic S-R latch except that the S and R inputs are only observed when the line C is high.
C means “control” or “clock”.
11
S
R
Q
C
Q
1
1
S`
R`
5.3 Storage Elements :LatchesSlide12
D Latch(Transparent Latch)
Adding an
inverter to
the S-R Latch,
gives the D Latch:
Note that there
are no “indeterminate”
states! (solves the S-R latch problem)
12
C
D
Q
Q
D
Q
C
Q
5.3 Storage Elements :LatchesSlide13
D Latch(Transparent Latch)
13
Q
D
Q(t+1)
0
0
0
0
1
1
1
0
0
1
1
1
Next state of Q
D
C
No change
X
0
Q=0, reset state
0
1
Q=1 , set state
1
1
5.3 Storage Elements :Latches
Qnext
=((D.C)’.Q’ current)’
Q’next
=((D’.C)’.Q current)’
Q t+1
D
0
0
1
1Slide14
The latch timing problemMaster-slave flip-flopEdge-triggered
flip-flopOther flip-flops
- JK flip-flop
14
5.4
Sequential Circuits :Flip-FlopsSlide15
The Latch Timing Problem
In a sequential circuit, paths may exist through combinational logic:
From one storage element to another
From a storage element back to the same storage element
The combinational logic between a latch output and a latch input may be as simple as
an interconnect
For a clocked D-latch, the output Q depends on the input D whenever the clock input C has value 1
15Slide16
The Latch Timing Problem (continued)
Consider the following circuit:
Suppose
that initially Y = 0.
As
long as C = 1, the value of Y continues to change!
The changes are based on the delay present on the loop through the connection from Y back to Y.
This behavior is clearly unacceptable.Desired behavior: Y changes
only once per clock pulse
16
Clock
Y
Clock
C
D
Q
Q
YSlide17
A trigger: The state of a latch or flip-flop is switched by a change of the control input.
17
Timing
5.4
Sequential Circuits :Flip-FlopsSlide18
The Latch Timing Problem
The key of proper operation is it to trigger it only during a signal
transition
(negative or positive)
A
solution to the latch timing problem is to break the closed path from Y to Y within the storage element
The commonly-used, path-breaking solutions replace the clocked D-latch with:a
master-slave flip-flopan edge-triggered flip-flop18
5.4
Sequential Circuits :Flip-FlopsSlide19
Master-Slave Flip-Flop
Consists of two clocked
D latches in series
with the clock on the
second latch
inverted
What happened when c=1
?The data from D input is transferred to the master .The slave is disabled .
Any change in the input change the master output ( Y ) but can’t effect the slave output .
19
C
D
Q
C
C
D
Q
D
Master
Slave
YSlide20
What happened
when C=0?The master is disabled .
The slave is enable
.
The value of ( Y ) is
transferred to the slave as input .
The output ( Q ) is equal ( Y ) .Conclusion:
The output of the F-F. can change only during the transition of clock from 1 to 0 or at Trigger by the negative edgeThe output is the value stored in the master stage immediately
before the negative edge.What about positive edges?
20
C
D
Q
C
C
D
Q
D
Master
Slave
Y
Master-Slave Flip-FlopSlide21
Timing
21
5.4
Sequential Circuits :Flip-FlopsSlide22
Graphic Symbols
22Slide23
Other flip-flops
23
Other F-Fs can be built using D F-F
There
are
four operation on a
F-F- set
to 1- Reset to 0
- toggle ( complement ) of Q - nothing
There are tow F-F
- JK F-FSlide24
JK Flip-Flops
24
D = JQ’ + K’Q
Q
t+1
K
J
No change Q t+1 = Q
00Reset to 0
10Set to 1
01Complement Q t+1= Q’
1
1Slide25
Characteristic Table
25Slide26
Characteristic Equations
26Slide27
27Slide28
State Equation
28Slide29
29Slide30
30Slide31
Analysis
This circuit consist of :2 D F-F A and B
Input x
Output Y
Q
t+1
= DA= D AB = D
B31Slide32
32Slide33
33Slide34
34Slide35
State Diagram
35Slide36
36
state
Input / outputSlide37
37Slide38
38Slide39
1 D F-F ( A )2 Input X , Y
Qt+1 = DD = A
X y
Analysis
39Slide40
40Slide41
41Slide42
2 JK F-F (A , B)Input x
Q t+1 = JQ’ + K’Q
42
AnalysisSlide43
43Slide44
44Slide45
45