Packaging Packaging Requirements PowerPoint Presentation, PPT - DocSlides

Download mitsue-stanley | 2018-03-13 | General Desired package properties. Electrical: Low. . parasitics. Mechanical: Reliable and robust. Thermal: Efficient heat removal. Economical: Cheap. Wire bonding. Only periphery of chip available for IO connections. ID: 649605

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Complete PC in MCM


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Slide1

Packaging

Slide2

Packaging Requirements

Desired package properties

Electrical: Low

parasiticsMechanical: Reliable and robustThermal: Efficient heat removalEconomical: Cheap

Wire bondingOnly periphery of chip available for IO connectionsMechanical bonding of one pin at a time (sequential)Cooling from back of chipHigh inductance (~1nH)

http://www.embeddedlinks.com/chipdir/package.htm

More about packaging:

Slide3

Chip to package connection

Flip-chip

Whole chip area available for IO connections

Automatic alignmentOne step process (parallel)Cooling via balls (front) and back if requiredThermal matching between chip and substrate requiredLow inductance (~0.1nH)

Slide4

Bonding Techniques

Slide5

Tape-Automated Bonding (TAB)

Slide6

New package types

BGA (Ball Grid Array)

Small solder balls to connect to board

smallHigh pin countCheapLow inductanceCSP (Chip scale Packaging)Similar to BGAVery small packages

Package inductance:

1 - 5 nH

Slide7

Flip-Chip Bonding

Slide8

Package-to-Board Interconnect

Slide9

Package Types

Through-hole vs. surface mount

From

Adnan Aziz

http://www.ece.utexas.edu/~adnan/vlsi-05/

Slide10

Chip-to-Package Bonding

Traditionally, chip is surrounded by

pad frame

Metal pads on 100 – 200 mm pitchGold bond wires attach pads to packageLead frame

distributes signals in packageMetal heat spreader helps with cooling

From

Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Slide11

Advanced Packages

Bond wires contribute parasitic inductance

Fancy packages have many signal, power layers

Like tiny printed circuit boardsFlip-chip places connections across surface of die rather than around peripheryTop level metal pads covered with solder balls

Chip flips upside downCarefully aligned to package (done blind!)Heated to melt ballsAlso called C4 (Controlled Collapse Chip Connection)

From

Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Slide12

Package Parasitics

Use many V

DD

, GND in parallel

Inductance, I

DD

From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Slide13

Signal Interface

Transfer of IC signals to PCB

Package inductance.

PCB wire capacitance.L - C resonator circuit generating oscillations.Transmission line effects may generate reflectionsCross-talk via mutual inductance

L

C

Package

Chip

PCB trace

L-C Oscillation

Z

Transmission line reflections

R

f =1/(2

p

(LC)

1/2

)

L = 10 nH

C = 10 pF

f = ~500MHz

Slide14

Package Parameters

Slide15

Package Parameters

Slide16

Package Parameters

2000 Summary of Intel’s Package I/O Lead Electrical Parasitics for Multilayer Packages

Slide17

Packaging Faults

Small Ball Chip Scale Packages (CSP) Open

Slide18

CSP Assembly on 6 mil Via in 12 mil pad

Void over via structure

Packaging Faults

Slide19

Miniaturisation

of Electronic Systems

Enabling Technologies :

SOC

High Density Interconnection technologies SIP – “System-in-a-package”

From ECE 407/507 University of Arizona

http://www.ece.arizona.edu/mailman/listinfo/ece407

Slide20

The Interconnection gap

Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends

IC scaling

Time

Size scaling

PCB scaling

Interconnect Gap

Advanced PCB

Laser via

From ECE 407/507 University of Arizona

http://www.ece.arizona.edu/mailman/listinfo/ece407

Slide21

The Interconnection gap

Requires new high density Interconnect technologies

IC scaling

Time

Size scaling

PCB scaling

Advanced PCB

Reduced Gap

Thin film lithography based

Interconnect technology

From ECE 407/507 University of Arizona

http://www.ece.arizona.edu/mailman/listinfo/ece407

Slide22

SoC has to overcome…

Technical Challenges:

Increased System Complexity.

Integration of heterogeneous IC technologies.

Lack of design and test methodologies.Business Challenges:Long Design and test cyclesHigh risk investmentHence time to market.Solution

System-in-a-Package

From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

Slide23

Multi-Chip Modules

Slide24

Multiple Chip Module (MCM)

Increase integration level of system (smaller size)

Decrease loading of external signals > higher performance

No packaging of individual chipsProblems with known good die:Single chip fault coverage: 95%MCM yield with 10 chips: (0.95)

10 = 60%Problems with coolingStill expensive

Slide25

Complete PC in MCM

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