Overview of Embedded SoC Systems ECE 448 Lecture 15 ECE 44 8 FPGA and ASIC Design with VHDL Required R eading P Chu FPGA Prototyping by VHDL Examples Chapter 8 Overview of Embedded ID: 1028953
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1. ECE 448 – FPGA and ASIC Design with VHDLOverview of Embedded SoC SystemsECE 448Lecture 15
2. ECE 448 – FPGA and ASIC Design with VHDLRequired ReadingP. Chu, FPGA Prototyping by VHDL Examples Chapter 8, Overview of Embedded SoC Systems Source Code of Exampleshttp://academic.csuohio.edu/chu_p/rtl/fpga_mcs_vhdl.htmlBasys 3 FPGA Board Reference Manual 7. VGA Port
3. Embedded Systems vs. General-Purpose Computing Source: ETHZ, Prof. Lothar Thiele
4. Types of Embedded SystemsLow-EndHigh-EndExample: microwave ovenFeatures: simple control functions & user interfaceImplementation: 8-bit single-chip microcontrollerExample: cameraFeatures:input/output, menu, storing image filespreprocessing & data compression Implementation:MicrocontrollerHardware accelerator
5. FPGA with Soft Processor Core = FPGA-Based System on Chip (SoC)Source: The Zynq Book
6. Simplified Hardware Architecture of an Embedded SoC Source: The Zynq Book Hardware AcceleratorI/ODevices
7. IP Cores (Intellectual Property Cores)blocks of logic used in developing FPGA or ASIC systemsessential elements of design reuse part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. ideally, an IP core should be entirely portable – that is, able to easily be inserted into any vendor technology or design methodologycan be developed by the device manufacturers, third-party vendors, or the users themselves
8. Classification of IP CoresHard cores - physical manifestations of the IP design; best for plug-and-play applications; less portable and flexible than the other two types of coresFirm (sometimes called semi-hard ) cores carry placement data but are configurable to various applicationsSoft cores exist either as a netlist (a list of the logic gates and associated interconnections) or hardware description language ( HDL ) code
9. What is Software/Hardware Codesign?Integrated design of systems that consist of hardware and software componentsAnalysis of HW/SW boundaries and interfacesEvaluation of design alternatives
10. Software vs. Hardware Trade-offsSource: A Practical Introduction to Hardware/Software Codesign
11. Why Codesign?
12. The Embedded SoC Design ProcessPartition the tasks to software routines and hardware acceleratorsDesign user custom IP cores if neededDevelop the hardwareDevelop the softwareImplement the hardware and software and perform testing
13. IP-Centered SoC Development Flow
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16. Elements of the Development Flowhardware platform specification file: contains the “definition” of the SoC design, including the processor configuration, memory size and structure, I/O peripheral cores used, memory address mapping, etc.BSP (board support package): a mechanism to encapsulate the system codes; a customized collection of device drivers and initialization routines that support a particular systemdevice driver: a set of routines that operate or control a particular peripheral device. A driver acts as a “translator” between the hardware peripheral and application programs and enables the application programs to access peripheral functions without needing to know precise details..elf file: the Executable and Linkable Format
17. Custom IP Core DevelopmentDesign a custom digital circuit to implement the computation algorithm or special functionalityDerive an interface to connect the circuit to the bus or interconnect structure of the vendor's IP framework.Develop a device driver to control the new hardware core and integrate it into vendor's software library
18. FPro SystemFPGA Prototyping” or “Fun and ProfessionalSimple. It defines a simple synchronous bus protocol and a straightforward device driver structure. Once a hardware circuit is developed, it can be converted to an IP core by adding a simple interface circuit and a device driver. Functional. It provides a variety of I/O peripherals and commonly used serial interfaces (UART, SPI, and I2C) and includes working device drivers. It resembles a bare-metal 32-bit microprocessor board and can implement real-world projects targeted for this type of boards.
19. FPro System (cont.)FPGA Prototyping” or “Fun and ProfessionalPortable. Except for the processor, FPro SoC's IP cores are developed from scratch in HDL and do not use any vendor's proprietary components. The bus protocol and device drivers are not tied to any specific commercial platform, either. Thus, the IP cores and software codes are portable and can be reused for different FPGA devices and prototyping boards.“Upward compatible.” The development follows rigorous and proven design principles and practices. These knowledge and skills can be applied in the future for more complicated commercial platforms and larger projects. In fact, the IP cores and drivers developed can be easily modified to be incorporated into existing commercial IP frameworks.
20. FPro System (cont.)FPGA Prototyping” or “Fun and ProfessionalFun. It can incorporate existing I/O modules and quickly develop a functional prototyping project. It can provide hardware acceleration capability and thus is more capable and more flexible than any microprocessor board. This give us an opportunity to develop interesting and challenging projects and make studying hardware more “fun”.
21. Platform Hardware OrganizationProcessor module32-bit-wide data path32-bit memory address spaceMemory-Mapped-I/O scheme for I/O accessFPro bridge and FPro bussimple synchronous bus protocol for the two subsystems MMIO (memory mapped I/O) subsystemthe memory and registers of the I/O peripherals are mapped to the same address spaceaccessing memory and I/O peripherals involves the same instructionsVideo subsystem coordinates the operation of video cores
22. Top-level diagram of an FPro system
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24. MMIO SubsystemIncludes a standard slot interface that conforms to the FPro bus protocolThe MMIO subsystem consists of a controller to select a specific slot and can accommodate up to 64 instantiated coresAfter being “wrapped” with an interface circuit, custom digital logic can be plugged into the FPro platform. About a dozen IP cores have been developed and integrated into the MMIO subsystem.
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26. Video SubsystemEstablishes a framework to coordinate the operation of video cores.A video core generates or processes the video data stream.The cores are arranged as a cascading chain. The data stream is pipelined and “blended” through each stage and eventually displayed on a VGA monitor. The video subsystem demonstrates the principles of handling stream data, in which data are generated continuously and passed through a chain of components for processing.
27. Software hierarchy of an FPro SoC system
28. Platform Software OrganizationA simple bare metal software schemeNo operating systemThe processor boots directly into an infinite main loopSoftware hierarchy of an FPro system contains a hardware layer, a driver layer, and an application layer A boot routine is associated with the processor. It performs the basic initialization process, such as clearing the caches, configuring the stack and heap segments, and initializing the interrupt, and then transfers control to the main program. The timer core and UART maintain a system time and assist displaying a debug message on the console.
29. FPro SoC Development Flow
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31. Modified Development FlowIn Step 3, only the processor module, which contains a processor core and RAM, is generated via the IP integration utility. We must manually construct the HDL code for the top-level system, which is composed of the instantiation of the previously generated processor module and the MMIO and video subsystems from Step 2.In Step 6, since only the processor module configuration is listed in the hardware specification file, only processor-related codes, such as the boot routine, will be included in the BSP library. We must manually examine the IP cores in the top-level HDL file and include the corresponding driver files in the application software project.
32. Modified Development FlowSince the processor module is the same most of the time, Steps 1 and 6 only need to be executed once. The generated HDL files and BSP library can be use in subsequent designs.
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34. Vanilla FPro System(Part II of the Textbook)