for SpaceWire Codec Simone Vagaggini 12 Marco Trafeli 1 Daniele Davalle 1 Lucana Santos 3 Roberto Ciardi 12 P ietro Nannipieri 2 L uca Fanucci 2 SpacE FPGA Users Workshop SEFUW 2023 ESTEC ID: 1038718
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1. 1High-Performance UVM Verification IP for SpaceWire CodecSimone Vagaggini1,2, Marco Trafeli1, Daniele Davalle1, Lucana Santos3, Roberto Ciardi1,2, Pietro Nannipieri2, Luca Fanucci2SpacE FPGA Users Workshop (SEFUW) 2023, ESTEC, Noordwijk, 14-16 March SpacE FPGA Users Workshop (SEFUW) 20231IngeniArs S.r.l., Via Ponte a Piglieri 8, Pisa, Italy2Dept. Of Information Engineering, University of Pisa, Via Caruso 16, Pisa, Italy3European Space Research and Technology Centre, European Space Agency, Keplerlaan 1, Noordwijk, The Netherlands
2. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
3. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
4. INTRODUCTION3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec,Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
5. INTRODUCTIONDeveloped by IngeniArs S.r.l.3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec, Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
6. INTRODUCTIONDeveloped by IngeniArs S.r.l.Funded by European Space Agency3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec, Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
7. INTRODUCTIONDeveloped by IngeniArs S.r.l.Funded by European Space AgencyActivity goals: Check the compliance of IP Cores with the SpW standard3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec,Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
8. INTRODUCTIONDeveloped by IngeniArs S.r.l.Funded by European Space AgencyActivity goals: Check the compliance of IP Cores with the SpW standardEvaluate the UVM advantages3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec, Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
9. INTRODUCTIONDeveloped by IngeniArs S.r.l.Funded by European Space AgencyActivity goals: Check the compliance of IP Cores with the SpW standardEvaluate the UVM advantagesProve the UVM applicability to space systems3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec, Fully compliant with Universal Verification Methodology (UVM) SpacE FPGA Users Workshop (SEFUW) 2023
10. INTRODUCTIONDeveloped by IngeniArs S.r.l.Funded by European Space AgencyActivity goals: Check the compliance of IP Cores with the SpW standardEvaluate the UVM advantagesProve the UVM applicability to space systems3Verification Intellectual Property (VIP) for Functional Verification of any SpaceWire Codec, Fully compliant with Universal Verification Methodology (UVM) Promotion of UVM-based Verification ApproachSpacE FPGA Users Workshop (SEFUW) 2023
11. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
12. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW Codec4SpacE FPGA Users Workshop (SEFUW) 2023
13. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW CodecFully compliant with Rev.1 of SpW Standard4SpacE FPGA Users Workshop (SEFUW) 2023
14. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW CodecFully compliant with Rev.1 of SpW StandardDeveloped in SystemVerilog HVL4SpacE FPGA Users Workshop (SEFUW) 2023
15. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW CodecFully compliant with Rev.1 of SpW StandardDeveloped in SystemVerilog HVLFully compliant with UVM Easily reusable and maintainable 4SpacE FPGA Users Workshop (SEFUW) 2023
16. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW CodecFully compliant with Rev.1 of SpW StandardDeveloped in SystemVerilog HVLFully compliant with UVM Easily reusable and maintainable Host interfacePackets and BC transmission and reception Configuration changes and readings4SpacE FPGA Users Workshop (SEFUW) 2023
17. UVM-BASED SPACEWIRE CODEC TWIN MODELEmulates the ideal behavior of a SPW CodecFully compliant with Rev.1 of SpW StandardDeveloped in SystemVerilog HVLFully compliant with UVM Easily reusable and maintainable Host interfacePackets and BC transmission and reception Configuration changes and readingsData-Strobe interface Communication with DUT or any system with SpW interface4SpacE FPGA Users Workshop (SEFUW) 2023
18. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUT 5SpacE FPGA Users Workshop (SEFUW) 2023
19. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization 5SpacE FPGA Users Workshop (SEFUW) 2023
20. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handling 5SpacE FPGA Users Workshop (SEFUW) 2023
21. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handlingAutomatic TX of NULLs when needed 5SpacE FPGA Users Workshop (SEFUW) 2023
22. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handlingAutomatic TX of NULLs when neededAutomatic recognition of all types of errors 5SpacE FPGA Users Workshop (SEFUW) 2023
23. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handlingAutomatic TX of NULLs when neededAutomatic recognition of all types of errorsNo actions needed by the user 5SpacE FPGA Users Workshop (SEFUW) 2023
24. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handlingAutomatic TX of NULLs when neededAutomatic recognition of all types of errorsNo actions needed by the user Higher level of abstractionOnly packets and BCs to be defined 5SpacE FPGA Users Workshop (SEFUW) 2023
25. UVM-BASED SPACEWIRE CODEC TWIN MODELDirect Communication with DUTAutomatic link initialization Automatic TX and RX credit handlingAutomatic TX of NULLs when neededAutomatic recognition of all types of errorsNo actions needed by the user Higher level of abstractionOnly packets and BCs to be defined Significant Simplification of the Verification ProcessSignificant Reduction in Verification Time and Cost 5SpacE FPGA Users Workshop (SEFUW) 2023
26. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
27. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelSpacE FPGA Users Workshop (SEFUW) 20236
28. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelData-Strobe Error InjectorSpacE FPGA Users Workshop (SEFUW) 20236
29. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelData-Strobe Error InjectorTwin LinkCommunication between two Twin ModelsSpacE FPGA Users Workshop (SEFUW) 20236
30. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelData-Strobe Error InjectorTwin LinkCommunication between two Twin ModelsSame stimuli of the Main Link SpacE FPGA Users Workshop (SEFUW) 20236
31. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelData-Strobe Error InjectorTwin LinkCommunication between two Twin ModelsSame stimuli of the Main Link Emulates the ideal behavior of the SpW LinkSpacE FPGA Users Workshop (SEFUW) 20236
32. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREMain Link Communication between DUT and Twin ModelData-Strobe Error InjectorTwin LinkCommunication between two Twin ModelsSame stimuli of the Main Link Emulates the ideal behavior of the SpW LinkSpacE FPGA Users Workshop (SEFUW) 2023Support automated verification of all possible simulation scenarios6
33. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREEnvironment ConfigurationSpacE FPGA Users Workshop (SEFUW) 20237
34. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREEnvironment ConfigurationAgentsDUTTwin ModelError InjectionSpacE FPGA Users Workshop (SEFUW) 20237
35. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREEnvironment ConfigurationAgentsDUTTwin ModelError InjectionTwin Link Data Collectors SpacE FPGA Users Workshop (SEFUW) 20237
36. UVM-BASED VERIFICATION ENVIRONMENT ARCHITECTUREEnvironment ConfigurationAgentsDUTTwin ModelError InjectionTwin Link Data Collectors ScoreboardSpacE FPGA Users Workshop (SEFUW) 20237
37. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
38. VERIFICATION CAMPAIGNDefined and implemented 153 testcases 100% of functional coverage of SpW Standard Rev.18SpacE FPGA Users Workshop (SEFUW) 2023
39. VERIFICATION CAMPAIGNDefined and implemented 153 testcases 100% of functional coverage of SpW Standard Rev.1Verification Campaign on IngeniArs SpW Codec IP Core8SpacE FPGA Users Workshop (SEFUW) 2023
40. VERIFICATION CAMPAIGNDefined and implemented 153 testcases 100% of functional coverage of SpW Standard Rev.1Verification Campaign on IngeniArs SpW Codec IP CoreVerification Campaign on ESA SpW Codec IP CoreBasic VHDL adapter has been developed8SpacE FPGA Users Workshop (SEFUW) 2023
41. VERIFICATION CAMPAIGNDefined and implemented 153 testcases 100% of functional coverage of SpW Standard Rev.1Verification Campaign on IngeniArs SpW Codec IP CoreVerification Campaign on ESA SpW Codec IP CoreBasic VHDL adapter has been developed8SpacE FPGA Users Workshop (SEFUW) 2023DUTCompliance with SpW StandardCompliance with SpW Standard Rev.1Code Coverage – StatementsCode Coverage - BranchesIngeniArs S.r.l. SpW Codec IP Core🗸🗸96.05%92.08%ESASpW Codec IP Core🗸X95.24%91.72%
42. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
43. UVM-BASED APPROACH ADVANTAGESMaintainability9SpacE FPGA Users Workshop (SEFUW) 2023
44. UVM-BASED APPROACH ADVANTAGESMaintainabilityAdd functionalities (extension)9SpacE FPGA Users Workshop (SEFUW) 2023
45. UVM-BASED APPROACH ADVANTAGESMaintainabilityAdd functionalities (extension)Update functionalities (override)9SpacE FPGA Users Workshop (SEFUW) 2023
46. UVM-BASED APPROACH ADVANTAGES10SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusability
47. UVM-BASED APPROACH ADVANTAGES10SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilityFrom a single functional block
48. UVM-BASED APPROACH ADVANTAGES10SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilityFrom a single functional block
49. UVM-BASED APPROACH ADVANTAGES11SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilitySeparation between Verification IPs developers and users
50. UVM-BASED APPROACH ADVANTAGES11SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilitySeparation between Verification IPs developers and usersUsability without deep knowledge of the VIPs architecture, SystemVerilog HVL and UVM standard
51. UVM-BASED APPROACH ADVANTAGES11SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilitySeparation between Verification IPs developers and usersUsability without deep knowledge of the VIPs architecture, SystemVerilog HVL and UVM standardVery user-friendly definition of new testcases
52. UVM-BASED APPROACH ADVANTAGES11SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilitySeparation between Verification IPs developers and usersUsability without deep knowledge of the VIPs architecture, SystemVerilog HVL and UVM standardVery user-friendly definition of new testcasesPossibility to buy VIPs developed by other companies
53. UVM-BASED APPROACH ADVANTAGES11SpacE FPGA Users Workshop (SEFUW) 2023MaintainabilityReusabilitySeparation between Verification IPs developers and usersUsability without deep knowledge of the VIPs architecture, SystemVerilog HVL and UVM standardVery user-friendly definition of new testcasesPossibility to buy VIPs developed by other companiesVisit IngeniArs Booth to prove our SpW Codec Verification IP
54. OUTLINEIntroductionUVM-based SpaceWire Codec Twin ModelUVM-based Verification Environment Architecture Verification CampaignUVM-based Approach AdvantagesResults and ConclusionsQ&A2SpacE FPGA Users Workshop (SEFUW) 2023
55. RESULTS AND CONCLUSIONS12Verification IP supporting a full test Campaign of any SpW Codec
56. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models 12Verification IP supporting a full test Campaign of any SpW Codec
57. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment Architecture12Verification IP supporting a full test Campaign of any SpW Codec
58. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment ArchitectureCompletely automated and self-checking 12Verification IP supporting a full test Campaign of any SpW Codec
59. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment ArchitectureCompletely automated and self-checking Supporting all communication scenarios provided by the SpW Standard12Verification IP supporting a full test Campaign of any SpW Codec
60. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment ArchitectureCompletely automated and self-checking Supporting all communication scenarios provided by the SpW StandardEmployed in verification campaigns:Up to 100% functional coverage of SpW Standard, Rev.1. 12Verification IP supporting a full test Campaign of any SpW Codec
61. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment ArchitectureCompletely automated and self-checking Supporting all communication scenarios provided by the SpW StandardEmployed in verification campaigns:Up to 100% functional coverage of SpW Standard, Rev.1. On IngeniArs S.r.l. SpW Codec IP Core12Verification IP supporting a full test Campaign of any SpW Codec
62. RESULTS AND CONCLUSIONSBased on SpW Codec Twin Models Double-Link Environment ArchitectureCompletely automated and self-checking Supporting all communication scenarios provided by the SpW StandardEmployed in verification campaigns:Up to 100% functional coverage of SpW Standard, Rev.1. On IngeniArs S.r.l. SpW Codec IP CoreOn European Space Agency SpW Codec IP Core12Verification IP supporting a full test Campaign of any SpW Codec
63. Fully compliant with UVM with advantages in terms of:MaintainabilityReusability in other projectsRESULTS AND CONCLUSIONS12Verification IP supporting a full test Campaign of any SpW Codec
64. Fully compliant with UVM with advantages in terms of:MaintainabilityReusability in other projectsReusable for Verification of any SpW Codec IP CoreVery user-friendlyKnowlegde of SystemVerilog, UVM and VIP Architecture not requiredRESULTS AND CONCLUSIONS13Verification IP supporting a full test Campaign of any SpW Codec
65. Fully compliant with UVM with advantages in terms of:MaintainabilityReusability in other projectsReusable for Verification of any SpW Codec IP CoreVery user-friendlyKnowlegde of SystemVerilog, UVM and VIP Architecture not requiredReusable for Testing of any DUT with SpW InterfacesRESULTS AND CONCLUSIONS13Verification IP supporting a full test Campaign of any SpW Codec
66. Fully compliant with UVM with advantages in terms of:MaintainabilityReusability in other projectsReusable for Verification of any SpW Codec IP CoreVery user-friendlyKnowlegde of SystemVerilog, UVM and VIP Architecture not requiredReusable for Testing of any DUT with SpW InterfacesRESULTS AND CONCLUSIONSSignificant reduction of verification time and costsSignificant increase of DUTs reliability13Verification IP supporting a full test Campaign of any SpW Codec
67. QUESTIONS & ANSWERS 14Thanks for your attention! For more information about SpW Codec Verification IP:Email:simone.vagaggini@ingeniars.commarco.trafeli@ingeniars.comdaniele.davalle@ingeniars.comCompany Website:www.ingeniars.comSpacE FPGA Users Workshop (SEFUW) 2023Visit IngeniArs Booth