Main componentsamprestrictions TLK2501 serializer deserializer pseudo random generator Genesys FPGA development board Multiplexer which have bandwidth ID: 912459
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Slide1
BER-tester for GEB board
Slide2Main components&restrictions
TLK2501
serializer
/
deserializer
/
pseudo
random
generator
Genesys
FPGA
development
board
Multiplexer
which
have
bandwidth
more
than
320 MHz
8-bit
counter
16
driver
chips
We
can
test
only
one
hybrid
connector
at
the
time
Test
line
speed
320MHz
Slide3TLK2501Can
serialize
and
deserialize
at
speed
of
16 x
clock
speed
.
Can
also
generate
PRBS(
Pseudo
Random
Bit
Sequency
)
PRBS is 2^7-1
lenght
bit
stream
Slide4How to calculate BER
Solution
1
We
feed
one
differential
pair
at
a
time
with
PRBS
sequence
and
its
inversion. At
the
other
end
of
data
lines
XOR
port
is
used
to
indicate
error
bits
and
feed
in
to
the
counter
.
After
PRBS
sequence
is
send
we
will
acquire
counter
value
to FPGA and
count
BER
value
.
This
approach
will
need
multiplexer
to
split
that
same
test
to
all
line
pairs
in
connector
.
We
probaply
also
need
serializer
to
convert
parallel
stream
from
counter
to
serial
form
.
Slide5Slide6How to calculate BER
Solution
2
We
feed
PRBS
sequence
to every
single line at
a
time
and
return
the
signal
with
coaxial
cable
to
the
FPGA
where
we
compare
sended
signal
with
the
signal
from
coaxial
cable
.
We
will
need
multiplexer
for
this
approach
also
.
There
is
possibilty
that
some
data
loss
is
happened
in
coaxial
cable
.
Slide7Slide8Problems
What
are
requirements
for
tester
How many lines
at
the
same
time
we
need
to
test
?
Do
we
need
to
know
exact
line
where
problem
is?
How to
display
results
?
Slide9Suggestions/Questions