SHAKTI Processor for Nuclear Reactor Applications - PowerPoint Presentation

1. SHAKTI Processor for Nuclear Reactor ApplicationsN.Anil, Satya Rajesh Medidi, M.Manimaran, T.Sridevi, & D.Thirugnana MurthyElectronics & Instrumentation GroupIndira Gandhi Centre for Atomic ResearchKalpakkam&IIT-M Team, CSE-Department.

2. AgendaDAE/IGCARI&C Systems for ReactorsClassification of I&C SystemsArchitectureComputer based I&C systems VME bus based 68020 CPU cardComponent Obsolescence /Solution SHAKTI ProcessorAdapting Shakti processor to I&C Systems of ReactorsSHAKTI based EID-CPU card designRoadmap10-10-20192

3. Department of Atomic Energy /IGCARDepartment of Atomic Energy (DAE)Indira Gandhi Centre for Atomic Research Bhabha Atomic Research Centre (BARC)Madras Atomic Power Station ( 2 x 230 MWe)Fast Breeder Reactor (500 Mwe)10-10-20193

4. Fast Breeder Reactor First of its kind in IndiaPool type ReactorPower : 500 MweFuel : UO2 -PuO2 Coolant : Sodium I&C SystemsMonitor & Control plant parametersProtect the plant & Personnel10-10-20194

5. I&C Systems for Nuclear Reactor In modern Nuclear Power Plants (NPP), Computer based systems are extensively used for Instrumentation and Control (I&C) systems.I&C systems provide protection, control, supervision and monitoring in NPPI&C systems are designed as per AERB Safety Guide lines (AERB-SG-D-10, AERB-SG-D-20 & AERB- SG D-25)Indigenous Design & DevelopmentQualification (EMI/EMC, Environmental & Seismic)Verification (Internal And External)ValidationAERB Clearance10-10-20195

6. Categorization of I&C systemSafety Critical Systems (SCS) SCS play a principal role in achievement of NPP safety by safe shutdown of the reactor followed by decay heat removal from the core and containment of radioactivity. Safety Related Systems (SRS) SRS play a complementary role in achievement or maintenance of NPP safety. The efficient operation of SRS reduce the demand on SCS thus enhancing the availability of plant operation. Non-Nuclear Safety systems (NNS) NNS play auxiliary or indirect role in the achievement or maintenance of NPP safety. They can be part of total response to an incident but not be directly involved in mitigating the physical consequences of the incident. 10-10-20196

7. Safety Critical SystemSafety Related SystemNNS System RTC-1RTC-2Switch Over LogicSystemAnalog/Digital Signal from PlantOutput Signal to PlantSignalMultiplierSC-2 data highwaySC-2 data highwayRTUAnalog/Digital Signal from PlantOutput Signal to PlantPlant data highwayRTC-1RTC-2RTC-3AnalogSignalSafety ActionDigitalOutputsSafety Logic(2/3)SignalIsolatorCore Outlet ThermocoupleSC-1 data highwaySC-1 data highwaySC-1 data highway10-10-20197Triple Modular Redundant architecture is followed by 2/3 voting logic for safety action Dual redundant system with hot standby configuration with Switch Over Logic SystemSingle Embedded systemI&C System Architecture

8. Distributed Architecture10-10-20198

9. I&C System Design CriteriaSimple in designHighly ReliableFault AvoidanceDe-ratingSystematic ApproachFault ToleranceRedundancyDiversitySingle Failure CriterionFail Safe designFault detection & IndicationOnline DiagnosticsTestabilityHigh AvailabilitySurveillanceIndependent V&V10-10-20199

10. Computer Based I&C SystemsCBS comprises of CPU card Analog Input /Output cards Digital Input /Output cards Motion Control Cards Input /Output Back Plane FT Power supply ModulesLoad SharingFed from Diverse FeederNo operating SystemImportant functions of CBS: Scanning the inputs from sensors Processing logics Diagnostics Generation of outputs for actuators/final control elements Sending the processed data for storage & display purpose 10-10-201910Software is fused in EPROM

11. Design and Development Methodology 10-10-201911

12. Typical I&C system cabinetEmbedded System 1DI & RO simulatorAI simulatorSwitch Over Logic SystemDevelopment system at Lab10-10-201912Embedded System 2

13. Need of SHAKTI Processor 10-10-201913

14. Criteria for Processor Selection for Safety ApplicationsNo bug listsAvailability from more than one vendorTrack record in the marketCompatibility with backplane busPreferably proven track record in Safety ApplicationsCPU card is designed with Motorola 68020 processor for Safety systems of reactor .10-10-201914

15. Obsolescence of Electronics System life Component life * There is no slowdown of the issue in the near Future(This corresponds to 1% of the electronic parts available in the market)1990 2020 2050100806040DOIEOLSystem life vs Component life NPPs designed to operate for 40 to 50 years.Electronic components used in CBS becoming obsolete in 10 to 15 years10-10-201915

16. Mitigation planReactive type - Lifetime buy, last time buy, aftermarket sources, identification of alternatives or substitute parts, emulated parts.Proactive type - Identifying and prioritizing selected non-obsolete parts that are at risk of obsolescence and identifying resolutions for them before they are discontinued.Manufactures - EOL data is true on to 58%10-10-201916

17. COST of Processor ObsolescenceTime, Money, and Development resources Porting application software Processor qualification Opportunity cost Board redesign Last-time buy options Phasing in new product“It is never about processor, It is all about ecosystem”10-10-201917

18. VME bus based CPU CardCPU : MC68020 @ 25MHzFPP : MC68882 @ 25MHzVME Controller : VIC 068AEPROM : 1MB, 16 bit widthSRAM with ECC : 2MB, 32 bit width, Battery backedEEPROM : 128KB, 8 bit width Control Logic : Altera MAX7256S CPLDVME Master Interface: A32:D32, A24:D16, A16:D16Serial Port : 4 No’sLocal Area Network: 2 No’s Hardwired TCP/IP Ethernet moduleWatchdog Timer : Programmable - ms to sec (10 ms – 5 secs), WDT Testability : on demand, Potential Free Contact O/P for status RTC : 1No Battery backedDisplay : 4 digit alpha-numericLED Indications : VME access, EEPROM access, WDT, RUN,DBE. 10-10-201918

19. Block Diagram of CPU Card (MC68020)10-10-201919

20. Solution for Processor Obsolescence?Obsolescence of processor used in CPU card creates demand not only on the hardware but also on the software used in the systemHDL based designs with open specificationOpen tool chain for application developmentVerification framework for open specificationsFPGA or ASIC routeIntegration with third party peripherals with IP cores10-10-201920

21. Why SHAKTI processor?Nuclear reactors are designed to operate for 50 years whereas I&C systems become obsolete within 15 years.To overcome processor obsolescence, open source RISC V ISA based SHAKTI soft core processor developed by IIT-M is considered for CBS of Fast Breeder Reactors. Open SpecificationVerification FrameworkExpertise (IIT-M)Obsolescence free road mapBackward compatibility10-10-201921

22. Roadmap For Shakti processor based system –IGCAR 10-10-201922

23. Proposal to Test SHAKTI Core SHAKTI processor based piggy back board was designed as a snap-in pin to pin replacement for existing MC68020 CPU base board. 10-10-201923

24. Piggy back boardPiggy back board is designed which acts as a snap-in pin to pin replacement for MC68020 on CPU base board without altering control glue logic, EDAC logic and VME Interface logic. Piggy back board consists of Artix 7 FPGA, associated power, reset, clock, level translation, debug circuitry and pin grid array for connecting to MC68020 CPU card. Power, reset and clock for piggy back board are derived from CPU base board. Power supply sequencing of core and input/output modules of FPGA is done by power circuitry. SHAKTI Processor and it's associated wrapper logic is being implemented in Artix 7 family FPGA from Xilinx Inc. 10-10-201924

25. EID - Shakti CPU with Piggy back boardArtix 7 FPGA ; Level translators ; JTAG programmabilitySerial Configuration Flash ROM (128MB)10-10-201925

26. Shakti core in useArithmetic TrapsAXI to MC68020Interrupt Handler10-10-201926

27. What should be little endian and what should be Big endianWe started with peripherals to be Big endianWe ended with Code memory to be Little endian and rest of peripherals to be Big endian10-10-201927

28. Wrapper Logic Acts as a bridge between AXI4 and Motorola bus interfaceEndianness translation to communicate with Big-endian slaves.Incorporates dynamic bus sizing which is a MC68020 feature.Converts 64 bit transactions to 32 bitProvides burst transfer support.10-10-201928

29. Wrapper Logic Read and write timings10-10-201929

30. Porting Typical I&C Application Software and testing10-10-201930

31. StartScan inputsRAM checkDiagnostic logicProcessingGenerate Control &interlock outputsIF timerexpiredGenerate soft outputsReceive soft Inputs / commandsInit peripherals, I/O cards IF receivedWait for config dataEnable watchdog timerLoad timer with 1/5 secRefresh watchdog timerFlow chart for Application Software10-10-201931

32. Functional Testing of SHAKTI CPU CardTesting CPU card for Display ,Delay functionsCommunication Testing RS232 Ethernet CommunicationTesting with I/O ModulesDigital Input /output CardAnalog Input /Output Card30 Channel AIC30 Channel DIC4 Channel AOC15 Channel DOC Porting NNS Applications and testing Porting SRS Application and Testing Testing the core with Test bench10-10-201932

33. Challenges in Porting Application S/WProcessor (Big Endian)Processor Specific Instruction(Assembly instructions)Constructs specific to Tasking C Cross compilerStructure PaddingUnaligned AccessInterrupt HandlingException HandlingA framework is developed to guide step by step modifications of the ED20 applications to make them compatible with the Piggyback CPU card. 10-10-201933

34. Assembly Instructions _CASM void enable_interrupts() {move.w #$2000,sr /*Enable Interrupts */}_CASM void disable_interrupts() {move.w #$2700,sr /*Disable Interrupts */}void enable_interrupts() {set_csr(mstatus, 0x00000008 /*Enable Interrupts */}void disable_interrupts() {set_csr(mstatus, 0x00000000 /*Disable Interrupts */}10-10-201934

35. Constructs specific to Tasking Remove the constructs specific to Tasking C Cross compiler#pragma sep_on class data #pragma sep_off_IH void ISR_dummy (void)10-10-201935

36. Structure paddingUse –fpack-struct attribute while compilingBy doing the above the compiler will pack the structure as Little endian.In all the applications developed in ED20 which use ethernet library convert the data into little endian before transmission. But in our case by packing the structure and because of the Little-endian nativity of the compiler it is already done, so there is no need of Big-endian to Little-endian conversion before transmission as the things are already taken care. So we can comment out the this redundant code.10-10-201936

37. Unaligned AccessSHAKTI core does not support unaligned access. The retry register in wiznet module is a 16 bit register located at Unaligned address 0x0017. Since MC68020 allows unaligned access in etherenet library of ED20 card 16 bit transactions are done to this register. But SHAKTI processor doesnot support Unaligned access, so the 16 bit transactions should be converted to byte transactions. Set_vector() -> has to be aligned10-10-201937

38. Hot Standby Architecture10-10-201938

39. Porting Typical SRS Application Application program that is intended to work on MC68020 CPU card was compiled and build with the RISC V tool-chain. The same was flashed in CPU board. Functionality and performance of the SHAKTI CPU card is evaluated with the existing CPU card. Full scale CPU card design in progressThoroughly verified SHAKTI processor based CPU card will be deployed in CBSs of nuclear power plants.Diversified System with SHAKTI CPU card & Motorola CPU cardHMI softwareSHAKTI Motorola SOLS 10-10-201939

40. SHAKTI BASED ed20 CPU card10-10-201940

41. Road Map4110-10-2019

42. References[1]. AERB SG D-1, 2003. Atomic energy regulatory board: safety classification and seismic categorisation for structures, systems and components of pressurized heavy water reactors. In: AERB Safety Guide No. AERB/NPP-PHWR/SG/D-1. AERB SG D-1, Mumbai, India[2]. AERB SG D-25, 2010. Atomic energy regulatory board: computer based systems of pressurized heavy water reactors. In: AERB Safety Guide No. AERB/NPPPHWR/SG/D-25. AERB SG D-25, Mumbai, India.[3]. M. Manimaran, A. Shanmugam, P. Parimalam, N. Murali, S.A.V. Satya Murty, 2015. Software development methodology for computer based I&C systems of prototype fast breeder reactor Nucl. Eng. Des 292 46–56.[4].T.Sridevi, A.Shanmugam, D.Thirugnana Murthy, S.Ilango Sambasivan, P. Swaminathan, "Software Lifecycle for Safety Critical Systems" , International Conference on Trends in Intelligent Electronics System , vol.II,p.563-566, Nov 2007[5].D.Thirugnana Murthy, T.Sridevi, SAV Satyamurty and P.Swaminathan, “Verification & Validation of Computer Based Safety Systems for Nuclear Reactors”, International Conference on Peaceful uses of Atomic Energy, Delhi, pp 158 – 160, 2009.[6].https://riscv.org/ [7] .https://shakti.org.in/[8]. https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html[9].“Forecasting electronic part procurement lifetimes to enable the management of DMSMS obsolescence”, P. Sandborn et.al, Microelectronics Reliability.10-10-201942

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