1 COMP541 Specifying Memories in - PowerPoint Presentation

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COMP541Specifying Memories in SystemVerilog

Montek Singh

Oct 9, 2017Slide2

Overview of ROM and RAM2Slide3

Read-Only Memory (ROM)Memory that is ‘permanent’often the data is “baked into” during fabricationthere are ROM flavors that allow updatesPROM, EEPROM, etc.updates are typically infrequent or sporadicTop-level view:k address lines2k data locations

n bits of data at each location

3Slide4

Read-Write Memory (RAM)Allows reads and writes with similar speedscalled “random-access memory” (RAM)as opposed to spools of tape  sequential accessTop-level view:k address lines2k data locationsn bits of data/locationdata input as well

Need a line to specify reading or writingtypically only one wire neededsometimes two separate ones

4Slide5

SystemVerilogBehavioral descriptions of:ROM, single-ported RAM, dual-ported RAM, etc.5Slide6

SystemVerilog: 1-port RAMRAM examplesingle-ported  one address (for reading and writing)whether read or written is determined by “write enable”clockall writes take place on clock tickreads are asynchronousi.e., output after a propagation delay without waiting for a clock tick6

clockaddrdin

dout

wr

1-port

RAMSlide7

SystemVerilog: 1-port RAMlogic [Dbits-1:0] mem [Nloc-1:0];always_ff @(posedge clock) if(wr) mem[addr] <= din;

assign dout = mem[addr]; 7

clock

addr

din

dout

wr

1-port

RAM

The

actual storage where data

resides

Write operation on clock tick if write enabled

Reading

is asynchronous, no clock involvedSlide8

SystemVerilog: 2-port RAMRAM example2 portsone read-write port (using addr1)one read-only port (using addr2)2 outputs: dout1 and dout2only one data input: din8

clock

read-write: addr1

din

dout1

wr

2

-port

RAM

read-only: addr2

dout2Slide9

SystemVerilog: 2-port RAMlogic [Dbits-1:0] mem [Nloc-1:0];always_ff @(posedge clock) if(wr) mem[addr1] <= din;

assign dout1 = mem[addr1];assign

dout2

=

mem

[

addr2

];

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clock

read-write: addr1

din

dout1

wr

2

-port

RAM

read-only: addr2

dout2

The

actual storage where data

resides

Write operation on clock tick if write enabled

Reading

is asynchronous, no clock involvedSlide10

SystemVerilog: MIPS register fileRegister file3 portstwo read-only ports (using ReadAddr1 and ReadAddr2)one write-only port (using WriteAddr)2 outputs: ReadData1 and ReadData2one data input: WriteDataspecial case: reading $0 always returns 0

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clock

ReadAddr1

WriteData

ReadData1

wr

3-port

register file

ReadAddr2

ReadData2

WriteAddrSlide11

SystemVerilog: MIPS register filelogic [Dbits-1:0] rf [Nloc-1:0];always_ff @(posedge clock) if(wr) rf[…] <= …;

assign ReadData1 = … ? … rf[…];assign

ReadData1

=

… ? …

rf

[…];

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clock

ReadAddr1

WriteData

ReadData1

wr

3-port

register file

ReadAddr2

ReadData2

WriteAddr

The

actual storage where data

resides

Write operation on clock tick if write enabled

Reading

is asynchronous, no clock involved

Skeleton only. You fill in the details (Lab

7)

.

Reading $0 must always return 0Slide12

SystemVerilog: memory initializationSpecify a file that contains initial valuesone value per line:hex or binaryuse $readmemh for hexuse $readmemb for binarylogic [Dbits-

1:0] mem[Nloc-1:0];initial $readmemh

(“

mem_data.mem

”,

mem

, 0, Nloc-1);

always_ff

@(posedge clock) …assign …

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Specifies the file that contains initial valuesSlide13

SystemVerilog: ROM exampleROM examplesingle-portedread-only, no writingno clock neededreads are asynchronousi.e., output appears after a propagation delay without waiting for a clock ticklogic [Dbits-1:0] mem [Nloc-1:0];initial $readmemh(“mem_data.mem”, mem

, 0, Nloc-1);assign dout = mem[addr];

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Read operation only, no writesSlide14

SummaryToday we looked at:ROM vs. RAMSystemVerilog templates for memories14