Timing Margin Recovery - PowerPoint Presentation

1. Timing Margin Recovery With Flexible Flip-Flop Timing ModelAndrew B. Kahng and Hyein LeeUC San Diego VLSI CAD Laboratory

2. OutlinePreliminaryMotivationRelated WorkSequential LP-based OptimizationExperimental ResultsConclusions and Future Work

3. Preliminary: Static Timing AnalysisTiming cornersMin corner: the corner where gate/wire delay is minimumMax corner: the corner where gate/wire delay is maximumTiming modesScenarios where different functions are performed in a designTest mode, function mode, etc.Types of analysesGraph-based analysis: Considers only the worst/best casePath-based analysis: Considers input vectors for more accurate analysis

4. Preliminary: Flip-Flop (FF) Timing ModelFF timing componentsSetup time: the minimum amount of time input data should be steady before clockHold time: the minimum amount of time input data should be steady after clockClock-to-q (c2q) delay: the delay of output from clockConventional timing model: Setup/hold time and c2q delay are fixed values

5. Motivation: Flexible FF TimingSetup/hold time/c2q delay is NOT a single value Various setup-hold-c2q sets can be used for timing analysis⇒ Flexible FF timing model⇒ Reduce pessimismsetupholdc2q1c2qn... setup-hold-c2q flexible model⇒ Tradeoff among setup/hold/c2q delay

6. Motivation: Why Flexible FF Timing?If data paths are independent of each other in PBA,Using fixed FF timing model can loose performance optimization opportunityFlexible timing model could reduce pessimism470ps480ps460ps470ps460ps480psFF3FF1FF2setup: 10psc2q: 20pssetup: 10psc2q: 20pssetup: 20psc2q: 10psTotal: 500psTotal: 500psTotal: 500ps20ps10ps10ps20ps 520ps? 500ps!

7. Related WorkSetup-hold time interdependencyCharacterization [7] [8] [10]Timing analysis [1] [2] [3] [4] [5] [6]However, no consideration of c2q delaySetup-hold-c2q interdependency [1]Propose a timing analysis method by exploiting flexible flip-flop timing modelHowever, iterative search can result in suboptimal solutionsOur work Based on setup-hold-c2q interdependencyLinear programming-based global optimizationMode/corner-specific timing analysis by exploiting flexible FF timing model

8. OutlinePreliminaryMotivationRelated WorkSequential LP-based OptimizationExperimental ResultsConclusions and Future Work

9. Problem FormulationObjective: Find the best combination of setup/hold time and c2q for each FF to minimize setup/hold violationsSolution space: 3d surface  not easy to obtain an accurate analytical model with three variables To reduce the dimension, we divide setup-hold-c2q optimization into: setup-c2q optimization + hold-c2q optimization setupc2qholdc2qC2q-setup-hold surfacesetupholdc2q

10. Problem Formulation: Sequential LPSolve two sub-problems sequentiallyThe solution from one problem ⇒ used as input to another problemThe sequence of solving problems can change depending on which problem is more criticalSetup-c2q optimizationMaximize setup slackSubject toc2q + dmax + Tsu + Ssu ≤ P c2q = f(Tsu)L ≤ Tsu ≤ UHold-c2q optimizationMaximize setup and hold slackSubject toc2q + dmax + Tsu + Ssu ≤ Pdmin + Sh > Thc2q = f(Th)L ≤ Th ≤ UWhere dmax/dmin : max/min data path delay, Tsu: setup time, Th: hold time, Ssu: setup slack, Sh: hold slack

11. Timing Signoff Across Corners/ModesSetup/hold time does not have to be a single value across corners/modes!Timing signoff across cornersMax delay corner  hold violation , setup violation ⇒ Select optimal setup time firstMin delay corner  setup violation , hold violation ⇒ Select optimal hold time firstTiming signoff across modesScan test mode  hold violation ⇒ Select optimal hold time first

12. New Timing Signoff: Max CornerSetup-c2q optimization is performed firstsetup-c2q optimization for max delay pathshold-c2q optimization for hold violated pathsAnnotate setup/c2q to each FF Annotate hold/c2q to each FF

13. CharacterizationSetup-hold-c2q curves are characterized with exhaustive SPICE simulationSetup-hold-c2q triplets are obtained at every 5ps of timing pointsUse a pulse as the input data to characterize setup/hold time interdependencysetup time: data rise to clock rise, hold time: clock rise to data fall, c2q: clock rise to q risec2qsetup timehold timeclockdatainputq outputdata slewclock slew(for rising edge triggered FF and rise input)

14. New Timing Signoff: Overall FlowExtract path timing informationLP formulation with flexible flip-flop timing modelSolve Sequential LP (STA_FTmax , STA_FTmin)Annotate new timing model for each flip-flopSolutionNetlist (and SPEF, if routed)Timing signoff with annotated timing

15. OutlinePreliminaryMotivationRelated WorkSequential LP-based OptimizationExperimental ResultsConclusions and Future Work

16. Experimental SetupTestcasesOpen source designs with 65nm foundry technologyCommercial flowLogic synthesis: Synopsys Design/DFT Compiler H-2013.03-SP3P&R: Cadence Encounter Digital Implementation System XL 10.1Timing signoff: Synopsys PrimeTime H-2013.06-SP2LP solver: CPLEX 12.5.1Our method is compared withConventional: Conventional fixed FF timing model[4]: Flexible setup/hold time with fixed c2q delayscTool: a commercial tool with setup-hold pessimism reduction functionality

17. Experiment ResultsResults of corner-specific timing analysis at max/min cornerIn mode-specific analysis, the summation of setup/hold slacks is improvedOur method fixes negative setup/hold time violations “for free”Worst setup slackWorst hold slack[ns]

18. ConclusionWe exploit a flexible flip-flop timing model: three-dimensional tradeoff among setup time, hold time and clock-to-q delayWe apply sequential LP-based approaches for multi-corner/mode timing signoffWorst slack improves by 48ps on average and by up to 130ps with 65nm technology (inverter delay = ~50ps)Future workDemonstration with advanced technologiesMore accurate timing model of setup-hold-c2q tradeoffCircuit optimization by exploiting FF timing model flexibility

19. Thank you!