fineDelaymacro halfFineDelaymacro Fdelaymacro The first three blocks by Amogh Halgeri the last block by Aditya Narayan CoarseFineDelaymacro Four flipflops to generate the coarse delay and ID: 1031123
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1. The Delay blocksCoarse_fineDelay_macrofineDelay_macrohalfFineDelay_macroFdelay_macroThe first three blocks by Amogh Halgeri, the last block by Aditya Narayan
2. Coarse_FineDelay_macroFour flip-flops to generate the coarse delay and fifteen delay blocks (each consisting of two DELAY_C’ elements) to generate fine delayCoarse delay is a multiple of the clock cycle period, and fine delay is multiple of propagation time through delay blocks
3. Two input bits to select Coarse delay (sel_CoarseFineDelay [1:0]) among the four possible delays Four bit input to select the fine delay (sel_fineDelay [3:0]) among the sixteen possible delaysThe select bits are decoded using combinational logic to decide what delay is to be introduced
4. Spectre simulation of the extracted layout– slow process ; temperature - 500 celciusThe minimum coarse delay – half a clock cycle. Clock is inverted to make it out of phase with incoming data signal. Thus the design is more robust (no race condition when data changes duty cycle from 35% to 65%, clk at 320 MHz, data at 40MHz)The minimum fine delay – zero (Not passing through any of the delay blocks), delay through each DELAY_C element – 600 to 800 ps.Spectre simulation –Slow process and temperature of 500 celcius
5. Fine delay controlTotal fine delayDelay2 – Delay1 – half clk. cycle period (delay through each element)00002.5532 -00014.45451.910300106.43091.976400118.44272.0118010010.33081.8881010112.36342.0326011014.3251.9616011116.32582.0008100018.32692.0011100120.1141.7851101022.09711.9851101124.00321.9349110025.911.91110127.841.93111029.771.93111131.8242.05Average delay through a delay block– about 1.9 to 2 nsThis is the delay through two DELAY_C elementsDelay due to delay elements, wiring, the AO2222 cells and other combinational logic.
6. FineDelay_MacroThe 30 delay cells and the decoder as depicted by cadence rtl compiler gui.
7. Same as the Coarse_fineDelay_macro block but without the flip-flops, and thus without the clock cycle delay.Each AO2222 cell basically ‘and’s four pair of inputs and ‘or’s the ‘and’ed outputs. Four such cells used for selecting sixteen possible delays.Each delay ‘block’ is serial combination of two DELAY_C cells.Fifteen delay blocks are used, thus giving sixteen possible delays (one is zero - delay)The four bit input ‘sel’ is decoded combinatorially before being used to select one of the possible sixteen delays.The delay introduced by this combinational path is approximately 1.5 ns (simulated by spectre at 500 C , conservative analysis).
8. Spectre simulation of the extracted layout– slow process ; temperature - 500 celciusFine delay controlTotal fine delayDelay2 – Delay1 00001.5363 -00013.70602.169700105.86652.160500117.72261.8561010010.06852.3402010112.04191.9734011014.13612.0942011116.2102.0739100017.5841.39100119.4871.903101021.10351.7165101123.1682.0645110025.00101.833110126.79151.7905111028.79242.0009111130.84242.050Average delay through a delay block– about 1.8 to 2.1 nsThis is the delay through two DELAY_C elementsDelay due to delay elements, wiring, the AO2222 cells and other combinational logic.
9. The 15 delay cells and the decoder as depicted by cadence rtl compiler gui.halfFine_Delay_macro
10. This block has fifteen delay ‘blocks’ each consisting of ONE DELAY_C cellApart from this difference, it is the same as fine delay macroDelay control possible in smaller steps (0.8 ns instead 1.9 ns)Makes use of AO2222 cells, and four bit input is decoded combinationally.halfFine delay controlTotal fine delayDelay2 – Delay1 00000.4854 -00011.46790.982500102.29351.3100113.098490.8049901004.05810.959601015.20981.151701105.97180.76201116.90850.936710007.90190.993410018.93431.032410109.77330.839101110.662050.8888110011.5250.8629110112.40980.8848111013.2930.8832111114.26360.9706
11. Fdelay_macro - Aditya NarayanSelects one out of four input clocks and adds a delay to that clock specified by the four bit select input (sel_fdelay[3:0]).Uses INVERTBAL_L cell instead of DELAY_C cell is the delay element. This provides a much smaller step delay (each ‘block’ has two cells and a rough delay of 0.1 ns) Each inverter adds a delay of around 50-60ps and a Mux adds a delay of 200-350psMux is used to select the clock to be transferred into the fdelay block (sel_FD [1:0] is the two bit select input)Thus clocks from 80 MHz to 640 MHz can be transmitted out by introducing the required delay in them.
12. Block Diagram of FDelay_Macro, additional buffer and inverters added to maintain signal integrity
13. Each inverter adds a delay of around 50-60ps and a Mux adds a delay of 200-350ps. The additional inverters (apart from the delay cells) are used to provide greater load driving capacity.
14. Spectre simulations – for TT processA delay of 112.8 ps between two delay elements