Ashley Good David Graziano Tim Meyer Ben Petersen Matt Saladin Advisors Joseph Zambreno Phillip Jones Project Plan Design and implement the original Nintendo Entertainment System NES in reconfigurable hardware ID: 644827
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Slide1
NES FPGA Emulation System
Ashley GoodDavid GrazianoTim MeyerBen PetersenMatt Saladin
Advisors
Joseph Zambreno
Phillip
JonesSlide2
Project Plan
Design and implement the original Nintendo Entertainment System (NES) in reconfigurable hardwareFPGA: Xilinx ML-507Xilinx development environment Develop the individual NES components in VHDL Slide3
Design Plan
System breakdownCPUPPUI/O requirementsControllers
Video output
Game access
ROM file via Compact FlashSlide4
Central Processing Unit
CPU components are completed and integratedALUIFIDBranch LogicSlide5
Central Processing Unit
Testing Plan
Tested
ALU
Instruction fetch/decode
CPU as a whole needs to be integrated and tested with ROM file as input
After CPU is fully tested, it will need to be integrated with the PPU and retestedSlide6
Picture Processing UnitSlide7
Picture Processing UnitSlide8
Picture Processing UnitSlide9
Picture Processing UnitSlide10
Things to be done
Integrate components Test in ModelsimTest on FPGAVGA outputFrom test program
From NES
Controller interface
Connecting to FPGA board
Accessing controllers from I/O pins on board
Reading a game file store on
CompactFlash
cardSlide11
Semester Plan and Schedule
2/25: Have the CPU and PPU completed and tested3/8: Full NES Modelsim testing3/15: VGA output from FPGA3/15: Controller Interface
3/15: Start on board testing
4/15: On board/full system testing
4/15: Poster
4/29: Design Report