A Fortran listing of the simulation program used to generate the data - PDF document

A Fortran listing of the simulation program used to generate the data in this paper is available upon request.- T)µG)G)DS)S)Individually or in combination, mismatch between these parameters may produce serious unbalance. For example, consider theL) from a clamped inductive load. The first parallelbranch contains the mismatched parameters causing the unbalance. The other ten branches are identical and, therefore, equallyshare load and gate current. Because of the relatively large number of identical parallel branches, typical values are used for the equivalent toGF: typical 1.75A/ V IDX DRAIN-SOURCE VOLTAGE, VDS VTV Figure 2(a): Combined Switching Plane Illustrating Active Region, Equation (1),Figure 2(b): IRF150 Data Sheet Active RegionTransfer Characteristics For Deriving Gain Factor(GF) and Threshold Voltage (VT 5152025 30 -25V J0C J = 250C J0C VID (3) The designer has several 'open loop' options that will reduce unbalance to acceptable levels without introducing complex or(4) It is possible to limit pulse turn-on current unbalance to approximately 15% for certain applications without any device(5) Switching transition energy ratios for wide ranges of unbalance are shown to typically be in the range 1.5 to 2.5 - the• restrict the dynamic load line to certain areas of the• use of a three parameter screening test with a 90% yield.positive temperature coefficient for MOSFET resistance. The thermal 'runaway' characteristic of other semiconductor tech- Unbalance GeneratorCurrent DifferentialEnergy (Loss) Differential steady-state & Limitedconduction dynamic & limitedturn-off dynamic & limitedturn-off nonenone nonenone Power Circuit: noneturn-on dynamicturn-on & turn-off Gate Driver: dynamicturn-on & turn-off unbalance has inherent limits provided the gate-to-source voltages are the same. Limit functions are derived for ON resistance, SourceThreshold Transconductance or Gain Factor g , GF ON Ressitance D 60 - 140% 70 - 130% approximately 90% of production batch0.7 V Table 3:® ¥DADA ·DA · ITKBJA125225-·· in Figure 5 breaks into a new family of lociin limit magnitude is slightly more than two-to-one for 2 N Unbalance Cause = 0.158GF 535%28%40%30%89%62% 'Static' Limits For Dynamic Current Unbalance, (IBBT°pulse current, the hotter device has a higher drain current for a particular V, but as the pulse develops, this device will have acompensate each other. 0 1.01.52.02.5 1.00.80.60.40.2 0.51.01.52.0 FACTOR: I / GFII ))D) 01.02.0 DEVICE NORMALIZING 1DD1DD (¥) I ¥¥DDV ¥¥DD ¥¥DD and L are 50V,respectively. Two sets of fouryzed. For each set, twovalues of L are = 20nh, L10%, a value that could be appropriate for the TO-3 package with a common lead to = lnh, L = 0.5%, a minimum could be associated with to the MOSFET chip. For each L, two basicare analyzed (Q and Q loci, VILVA BRANCHBRANCH #1#2 N110 23V 2.451.75A/V 2 Q200 1002000100200 39% 'STATIC' LIMIT Q0 49% 'STATIC' LIMIT Q0 20(57%)=2.45A/VT1 Q 2 000 1002000100200 12LXGAIN FACTORLX0 Q 2 Q Q1 Q DeviceV #12.02.451500.200. #24.01.053800.500. Turn-OnTurn-Off DDETmmJDDETmmJ LSXQ1Q2Q1 1Q2Q1Q2 Data Sheet10% 1200/150610/130 0.5%25.9 490/100VZ 10%8.4 740/420410/260 0.5%8.4 620/420320/220, #1/#2) Vs. L Transition Energy ONOFF / L 1Q2Q1Q2 210/18051/19540/580320/340 110/676/3470/520270/270, current unbalance is approximately 15% for N = 2 and 33% for N = 11. For L Turn-OnTurn-Off NLS / LX Q1Q2Q1 1Q2 210%5.0 (14%)5.9 (17%)220/170 540/580360/300 0.5%0.8 (2%)0.3 (1%)88/85 490/500270/280 1110%10.2 (29%)12.5 (36%)280/220 560/580410/340 0.5%1.4 (4%)0.5 (1%)90/87 490/500260/270 Current (Energy (E, #1/#2, Microjoules) Unbalance Due to Common Source Inductance Turn-OnTurn-Off DDIETET LS / LX 1Q2Q1Q2Q1Q2 5.0 (15%)3.1 (9%)100/6938/29390/460320/350 8.2 (23%)3.7 (11%)23/155/4290/470220/350I, %) and Transition Energy (E , #1, #2, microjoules) Unbalance Due to De-Coupling, Resistance (R Table 15 lists typical values of ETC Duty CycleLowHigh High1~1 Low~1�� 1A - eliminate the cause by matching the parameters listed in I(c) (i), (ii) and (iii) above, i.e. realize a balanced systemB - modify the power circuit to compensate for or cancel the effect of the mismatch, i.e. minimize the magnitude ofC - modify the gate driver to offset the effects of parameter mismatch, i.e. minimize the duration of unbalance. 406080 I I IT1 406080 I I IDT2 (1) relatively small increase in L(2) locate a diverter circuit that will limit the peak drain-to-source voltage and absorb more than the resulting increaseMOSFET switch operates at. 040002004006008000200400600800 iD2QSQ iiD1iDIL V VV i 02004006000200400600800 (ii) Turn-Off • MOSFET gate-to-source and Miller capacitance mismatch are not significant provided decoupling resistance is• Branch inductance and decoupling resistance (for above recommendation) mismatch are not significant.• Matching common source inductance (for L• Screening MOSFET R• MOSFET threshold voltage and gain factor (transconductance) screens are effective for dynamic current balance.• Additional series resistance, current balancing transformers or feedback to the gate driver are not needed for current• Increasing common source inductance assists dynamic current balance. This also increases transition energy.• Minimizing decoupling resistance assists dynamic current balance by reducing differential gate-source voltages• Increasing the dynamic load line Q value assists dynamic current balance. This reduces transition energy, butStarting from a general set of parameter mismatch to balance turn-on current, minimize L 00406080 i = 70A iBiiD1EET2 200400 TT + 200 (A2) RIKRIKDJADJA12512512252252/N(A6) RIKNIIDJA1251251225225 RRKNRRKNNIKRNIRNIJABJAB1252251252252252251251225Dividing (A8) by Idesign junction-to-ambient temperature rise for RTKNTKBJA2251252225125 /N (B6) IGFVVGFNGFNGFVNGFNGFINGFGFVDGSTTBT11121212111[()]()[()]() (B8) ()() (B10) DDM (B11) BDM (Bl2) b map the dynamic load line deflection and the increase in turn-on energy for increased values of LSX.circuit inductance, LXthe increased device transition energy. +-+---+ - VSVIL +-+-+- VSILV --+-+-++-V0 V ON = VSSS ½½V½½VSSS ½½V½½LXSSiV0SS ½½V½½V0SS ½½V½½LXSSiXLX SX25002040OHMICiDQ1Q230%Q0LSXQ0Q1Q2V Figure C3(a) & C3(b): 20000400800Q0Q1LSXQ2 LXTRANSITION