CBC3: A CMS micro-strip - PowerPoint Presentation

1. CBC3: A CMS micro-strip readout ASIC with logic for track-trigger modules at HL-LHCSTFC RAL: Mark Prydderch, S. Bell, M. Charrier, L. Jones, P.Murray, D. Braga†Imperial College: G. Auzinger, J. Borg, G. Hall, M. Pesaresi, M. Raymond, K. UchidaUniversity of Bristol: J. Goldstein, S. Seif El Nasr †Now at Fermilab

2. Background CBC3 Features CBC3 Single Chip Testing Future work Summary & ConclusionOutline2

3. Outline2 CBC3 Features CBC3 Single Chip Testing Future work Summary & Conclusion Background

4. 2S Modules: Two-strip double-layers7680 modules~31M channels8 CBCs per sideFront EndHybridService HybridCIC1 per sideDouble-LayerSi Strip DetectorsDC-DCConverterLP-GBT &Optical VTRx10 cm5 cm127 Strips/CBCEach 2S Module:Sensor Area ~100 cm216 CBCs, each reading 254 strips (127 from top & bottom sensors)4064 Channels in totalReadout both L1 triggered data & Primitive trigger dataWhere to find the CBC3

5. CBCFlex PCB Hybrid500µm CF SupportCF StiffenerBridgeSilicon sensorsOuter Sensor(Correlation Layer)Inner Sensor(Seed Layer)Particle Track(High pT)Particle Track(Low pT)Hit StripCorrelation WindowYESNoRf1.8  4 mmHigh-PT tracks (Stubs) can be identified if cluster centre in top layer lies within a correlation window in R-Φ (rows)pT cut given by: module radius (z), sensor separation and correlation windowHit StripBasic 2S Module Concept4InnerOuter½ ModuleBend

6. Common features:I2C InterfaceDC – DC Converter (2.5V  1.2V)LDO for analogue powerBandgap for biases256 deep Pipeline40MHz Serial L1 Data Output10.785 mmCBC1 (2011)128 Dual polarity channelsWire BondedAPV style serial command schemeAnalog Test InputsCBC2 (2013)254 Dual polarity channelsC4 Bump BondedDirect command inputsOn-chip Test Pulse Generator with DLLCorrelation logic for stub formationCluster width veto40MHz serial readout of Stub DataAnalogue Mux for bias monitoringFront-end circuit improvementsImproved DC-DC converter (CERN)CBC1 & CBC24 mm7 mm4.785 mm5CBC 1CBC 2

7. Outline CBC3 Features Background CBC3 Single Chip Testing Future work Summary & Conclusion

8. AnalogueFront End512 DeepPipeline (12.8µs)+32 DeepBufferTest Pulse GeneratorBiasGeneratorSlow ControlStub Finding & Bend Calculation Logic1254I2C (1 MHz)320 MHz ClockVDDD1.2VBandgapVDDA 1.0 VCluster Width VetoHit DetectvthvthvthvthDLL40 MHzDomainNearest Neighbour Signals (NNS)NNSCBC3 ArchitectureChannel Mask320 Mbps SerialCommand inputStub & TriggeredData on 6 SLVS OutputsConfiguration Registers320 MHzDomainProgrammable Phase 40 MHz DomainOverflowOR 2546LDOData PacketAssembly &TransmissionStub Gathering LogicFast ControlBend lookup TableL1 CounterLayer Swap40 MHz RecoveryDLLChip ID & BGe-FusesPISO Shift Register

9. Single Polarity (electrons)Faster Pulse Shape3x Bias current range for larger detector capacitancesNew preamp regulated cascode to eliminate “Shadow effect” observed when many channels fireNew postamp feedback bias scheme (not shown)Current neutral comparatorAdjusted for 1V operationCBC3 Front End ChangesEliminate common-mode effects observed when many channels fire7

10. Stub LogicLayer SwapStub Gathering LogicHit DetCWDCorrelation& BendHit DetCWDS127C127Hit DetCWDCorrelation& BendHit DetCWDS1C1122532548-bit address5-bit bend x Max 3 StubsC=Correlation Layer Channel (Outer)S=Seed Layer Channel (Inner)CS2 & 4 strip clustersgive ½ stripStub AddressClusters >4Strips rejectedProgrammableCorrelationWindowCSProgrammableWindow Offset8Stub Priority LogicStub Address LogicMuxCorrelation bit& 5-bit bendBendBend

11. Fast Command InterfaceB<7>320MHzClockFast CommandInputRecovered40MHz ClockB<6>B<5>B<4>B<3>B<2>B<1>B<0>B<7>B<6>B<5>B<4>B<3>B<2>B<1>B<0>Fast Command(Internal)1 1 0Sync PatternXFast CommandStopBitSync PatternFast CommandFast CommandB7B6B5B4B3B2B1B0Fast Reset11010001Trigger11001001Test Pulse Trigger11000101Orbit Reset11000011Orbit Reset & Fast Reset11010011Orbit Reset & Trigger11001011Orbit Reset & Test Pulse Trigger11000111XXX1101XXXX25ns9

12. Outline CBC3 Features Background CBC3 Single Chip Testing Future work Summary & Conclusion

13. 13All CBC3 results so far are from a wire-bonded single chip setup(chips diced from first wafer)~Same setup used for ionizing and SEU tests CBC3InterfacecardTests carried out at ImperialBack-edge column of pads reserved for wafer probing - can be wire-bondedSingle Chip Test PCBAdditionalGND bonds10

14. 320 Mbps triggered output dataFrame length 950 nsHeader contains the pipeline address that the data originates from + L1 counter value (reset every orbit)SLVS output driverOn-chip test pulse used2 start bits2 error bits10 ns /div.2 test pulse bitsTriggered Data Readout2 start bits9 Bits pipeaddress9 bits L1 countLatency error254 bits strip readout dataTotal frame length (active data) = 276 bits = 862.5 nsBuffer overflowMSB firstchannel 1 first950 ns0 packedto 950nsTriggered data packet formatTriggered data captured on oscilloscope11876543210876543210

15. Sync pulse every 25 nsec + stub 3 bend info Stub 1 & 2 bend info Stub 3 address Stub 2 address Stub 1 address Stub data packet formatStub Data ReadoutSYNCStub AddressesStub Bends& FlagsMSB firstS1<7>S1<6>S1<5>S1<4>S1<3>S1<2>S1<1>S1<0>S2<7>S2<6>S2<5>S2<4>S2<3>S2<2>S2<1>S2<0>S3<7>S3<6>S3<5>S3<4>S3<3>S3<2>S3<1>S3<0>B2<3>B2<2>B2<1>B2<0>B1<3>B1<2>B1<1>B1<0>SYNCFlagsOR254SoFB3<3>B3<2>B3<1>B3<0>8 Clock cycles @ 320MHz (25ns)Stub Data <5>Stub Data <3>Stub Data <4>Stub Data <1>Stub Data <2>SLVSSLVSSLVSSLVSSLVS0010Stub (trigger) data captured by DAQ25 ns00100010SYNC12

16. 16We can measure the analogue pulse shapes by sweeping the charge injection time for different comparator thresholdsbm = 1bm = 8bm = 15[mVolts][ns]MeasurementSimulationGood pulse shape agreement between simulation and measurementCBC3 pulse shape duration reduced (cf. CBC2) to achieve single BX resolutionVarying 4-bit beta multiplier setting gives some control over output pulse durationVCTHcomparatoriinamp.Front End Pulse Shape132.5 fC injected

17. AfteroffsetstuningVCTH units [~mV]CountsCountss = 0.3 VCTH units ~ 50 eSweep global comparator threshold to generate s-curvesTune offsets to compensate for channel-to-channel differencesAfter tuning, the channel offsets distribution has σ of ~50 electrons All ChannelOffsets setto samevalueHistogramOf S-curvemid-pointvaluesVCTHComparatoriinOffsetadjustAmp.VCTH [V]I2C valueINL & DNL < 1LSBVCTH now generated by 10-bit resistor ladder DACS-curves & Channel Offsets Tuning14

18. ENC [electrons]Cexternal [pF]T=+30T=-20SimulationSingle chip test board has provision to bond 8 inputsCBC3 bump-bond pads have wire-bondable finish (unlike CBC2’s C4 pads)Can make use of this to inject external charge and add external capacitance to measure noiseSingle-chip setup noise performance looks ok (even with a wire-bonded chip)Measured Gain 47 mV/fC with ~5% spread350 µW/Channel Analogue160 µW/Channel DigitalNoise, Gain & Power8 AnalogueInputsPower &Digital I/OCBC315Measured

19. Ionising Radiation Tests at CERN:CBC3 irradiated to > 400 kGyNo change in performance (noise, pedestals,…)Transient increase in digital current in few Mrad region falls back to pre-irradiation values at higher dosesCurrent dominated by leakage in stub-finding logicAt HL-LHC dose-rate (9 Gy/hr) & temp (-15o) the effect will be negligible (pessimistic assumptions)~1.3% max. increase in module power consumptionRadiation Studies16CBC3InterfacecardSEU Tests on Proton Beam at UCL (Louvain):~15 hours of beam corresponds to ~1000 hours @ HL-LHCDetected 25 single bit flips altogether in I2C registers~ 8x reduction cf. CBC2Corresponds to ~1.5 bit-flips/day per chip at HL-LHC (pessimistic assumptions)Considering periodic reconfiguration vs minor changes to circuitCBC3 at UCL proton beam

20. Outline CBC3 Features Background CBC3 Single Chip Testing Future work Summary & Conclusion

21. Future WorkTest the CBC3 2 chip ModuleVerify performance when bumpedVerify nearest neighbour logic for StubsCBC 3.1Add invalid Stub rejection functionAdd Nearest Neighbour I/O test feature for wafer testing completenessImprove Triggered Data Serialiser robustness to Clock 40 DLL phase shiftsImprove configuration register SEU robustness (TBC)Manufacture CBC3.1Test CBC3.1Production Wafers17

22. Outline CBC3 Features Background CBC3 Single Chip Testing Future work Summary & Conclusion

23. Summary & ConclusionSuccessful final full-size prototype of the new Outer Tracker ASICCBC3 working to specificationRe-designed Stub identification & new output data chain both functionalPipeline: Corrected the radiation induced effects seen on CBC2Improved SEU performance of configuration registers8 wafers tested with 5 sent to PacTech for bumpingSome functional modifications needed for the production versionAcknowledgementsThank you to all our colleagues at CERN, Bristol (UK), Gdańsk UoT (PL), KIT (DE), IPHC (FR), for their contributions185.035 mmCBC 310.802 mm

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25. EXTRAS

26. Important for hybrid developmentImportant for module construction studiesBoth mini and full-size modules constructedTest beam demonstration of pT module conceptFull size 2S module prototypeAngular scan of module in beamTranslatedto r=75cm layereffective pT cut~ 2.2 GeV/cM.Pesaresi5cm strip length (90um pitch)2.8mmspacing2CBC2 mini-moduleCBC210 x 10 cm2 sensors(n-in-p)2 x 8 CBC2 chipson flex hybrids26CBC2 Testing6

27. Detector Type: Silicon StripSignal Polarity: both (electrons and holes)Strip length: 2.5 – 5cmStrip Capacitance: < 10pFCoupling: AC or DCDetector leakage: up to 1uA leakage current compensationNoise: <1000e-RMS for 5pF sensor capacitanceOverload recovery: normal response within ~ 2.5µs after 4pC signalPower: ~500µW / channel (for 5pF strips)Power supply: 1.1 V (front end supplied through LDO to get supply noise rejection)Gain 50mV/fCDynamic range: Linear up to 4fC Timewalk: <16ns for 1.25fC and 10fC signals with comp. thresh. set at 1fCCBC2 Front End Specifications

28. CBC 14 mm7 mmCBC 24.785 mm10.785 mm5.035 mm10.802 mmCBC 3The CBC Family Tree

29. PipelineControlFront EndAmplifiers512 DeepPipeline (12.8µs)+32 DeepBufferTest Pulse GeneratorBiasGeneratorSlow ControlOffset Correction & Stub Identification1254I2C (1 MHz)VDDD1.2V+/-10%BandgapLDOVDDA 1.0 VCluster Width VetoChannel MaskvthvthvthvthPISO Shift RegisterComparatorsPISO Shift RegisterFast Control 254 Channels DLLNearest Neighbour Signals (NNS)CBC2 ArchitectureHit DetectConfiguration RegistersOR 254OR 127Stub Data @ 40MHzORSelectCoincidence ORNearestNeighbourSignals

30. CBC3 Features10.802 mm5.035 mm254 single polarity channels (electrons) Bump Bonded with extra column of pads for Wafer Test.Enhancements to analogue front endEnhanced Hit Detect with programmable HIP suppressionChannel Masking  For both Pipeline & Stub LogicPipeline SRAM radiation hardened Pipeline increased to 512 deep (12.8µs)320 MHz readout of Triggered Data from PipelineUp to 1MHz L1 Trigger rate capableL1 CounterLayer swap multiplexing of odd & even channelsProgrammable Cluster width veto (up to 4 strips wide)Correlation logic with half-strip resolution for stub IDCorrelation Window Offset  4 programmable regionsStub Gathering Logic  Outputs up to 3 stubs plus OverflowBend LUT for 5 to 4 bit bend translation320 MHz readout of Stub Address & Bend Data

31. CBC3 Features10.802 mm5.035 mm320 MHz serial Fast Command Interface (FCI)On-chip 40MHz clock recovery from FCI40MHz DLL for BX timing adjustment.On-chip Test Pulse Generator with DLLAnalogue Mux for bias monitoringLDO tweaked for 1.1V operationImproved DACs for All CMOS Bandgap (CERN)E-Fuses for Chip ID & Bandgap trimmingI2C Interface  Repeated Start & Hang up reset addedWhitaker Latches for configuration registersDROPPED  DC-DC converter

32. Hit DetectLogical OR OutputHIP Suppressed after count of 340MHz clock periodComparator OutputFixed-Pulse-Width Output40MHz Sampled OutputHIP Suppressed Output123ComparatorToPipelineToStubLogicHIP CountValue(3 bits)HIP EnableStub Logic Select (2 Bits)Pipeline Select (2 Bits)MuxOR Select(1 Bit)40MHz DLL adjusted clockFixed Pulse WidthMuxMuxCompareLogicI2C Reg3 BitCounterChannelMaskHIP Suppression40MHzSampled9

33. Stub Logic (2)Cn = Correlation Bit (1b) Bn = Bend Information (5b)An+1+Bn+1An+1½+Bn1½An+2+Bn+2An+½+Bn+½An+BnC1C1½C2½C2C3B1B1½B2½B2B3An+1An+1½An+2An+½AnMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxPrioritySelectionLogicStub Overflow FlagNOTE: An = Stub Address (8 bits generated locally)Bn+2MuxMuxMuxMuxMuxCnCn+½Cn+1½Cn+1Addr & BendFrom higherno. channelsInputsfromStub Finding LogicStub Data Outputs3 x 8 bit Stub AddressesBendLook-upTableStub Data Packet AssemblerS1<7>S2<7>S3<7>B2<3>SyncS1<6>S2<6>S3<6>B2<2>ErrorS1<5>S2<5>S3<5>B2<1>OR254S1<4>S2<4>S3<4>B2<0>SoFS1<3>S2<3>S3<3>B1<3>B3<3>S1<2>S2<2>S3<2>B1<2>B3<2>S1<1>S2<1>S3<1>B1<1>B3<1>S1<0>S2<0>S3<0>B1<0>B3<0>SLVS<1>SLVS<2>SLVS<3>SLVS<4>SLVS<5>I2C3 x 4 bitBend Data3 x 5 bitBend Data10

34. Stub Logic (2)Cn = Correlation Bit (1b) Bn = Bend Information (5b)An+1+Bn+1An+1½+Bn1½An+2+Bn+2An+½+Bn+½An+BnC1C1½C2½C2C3B1B1½B2½B2B3An+1An+1½An+2An+½AnMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxPrioritySelectionLogicStub Overflow FlagNOTE: An = Stub Address (8 bits generated locally)Bn+2MuxMuxMuxMuxMuxCnCn+½Cn+1½Cn+1Addr & BendFrom higherno. channelsInputsfromStub Finding LogicStub Data Outputs3 x 8 bit Stub AddressesBendLook-upTable3 x 4 bitBend Data3 x 5 bitBend DataStub Data Packet AssemblerS1<7>S2<7>S3<7>B2<3>SyncS1<6>S2<6>S3<6>B2<2>ErrorS1<5>S2<5>S3<5>B2<1>OR254S1<4>S2<4>S3<4>B2<0>SoFS1<3>S2<3>S3<3>B1<3>B3<3>S1<2>S2<2>S3<2>B1<2>B3<2>S1<1>S2<1>S3<1>B1<1>B3<1>S1<0>S2<0>S3<0>B1<0>B3<0>SLVS<1>SLVS<2>SLVS<3>SLVS<4>SLVS<5>I2C110

35. Stub Logic (2)Cn = Correlation Bit (1b) Bn = Bend Information (5b)An+1+Bn+1An+1½+Bn1½An+2+Bn+2An+½+Bn+½An+BnC1C1½C2½C2C3B1B1½B2½B2B3An+1An+1½An+2An+½AnMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxMuxPrioritySelectionLogicStub Overflow FlagNOTE: An = Stub Address (8 bits generated locally)Bn+2MuxMuxMuxMuxMuxCnCn+½Cn+1½Cn+1Addr & BendFrom higherno. channelsInputsfromStub Finding LogicStub Data Outputs3 x 8 bit Stub AddressesBendLook-upTableStub Data Packet AssemblerS1<7>S2<7>S3<7>B2<3>SyncS1<6>S2<6>S3<6>B2<2>ErrorS1<5>S2<5>S3<5>B2<1>OR254S1<4>S2<4>S3<4>B2<0>SoFS1<3>S2<3>S3<3>B1<3>B3<3>S1<2>S2<2>S3<2>B1<2>B3<2>S1<1>S2<1>S3<1>B1<1>B3<1>S1<0>S2<0>S3<0>B1<0>B3<0>SLVS<1>SLVS<2>SLVS<3>SLVS<4>SLVS<5>I2C3 x 4 bitBend Data3 x 5 bitBend DataMux1110

36. Kirika Uchida, Johan BorgTest in proton beam at UCL (Louvain)Looking for improvements in I2C register SEU sensitivity cf. CBC2~15 hours of beam corresponds to ~1000 hours @ HL-LHC*Detected 25 single bit flips altogether in I2C registers~ 8x reduction cf. CBC2Corresponds to ~1.5 bit-flips/day per chip at HL-LHC (pessimistic assumptions)Small number, but with ~120,000 chips in CMSConsidering periodic reconfigurationImprovement by minor changes to circuit also under consideration* SEU cross-section for 62 MeV protons is equivalent to average cross-section at the HL-LHCFlux ~75x HL-LHCSingle Event Upset testsCBC3Interfacecard

37. InterfacecardThorough test procedure covering digital & analogue sectionse-fuse technology used to program individual chip ID & tune on-chip bandgapShared wafer (SCA for PS modules)8 CBC3 wafers have been probed186 chips per waferWafer Probing5 delivered to PacTech for bump-bond processing and dicing Average Yield of wafers ~85%

38. S. Seif El Nasr-StoreyG. AuzingerFor more details see https://indico.cern.ch/event/653699/CBC3 irradiated to >40 Mradno change in performance (noise, pedestals,…)Transient increase in digital current in few Mrad region falls back to pre-irradiation values at higher dosesMasking studies show current dominated by leakage in stub-finding logic (many non-enclosed NMOS devices)Maximum increase depends on dose-rate and temp.Campaign of irradiations at different dose-rates and temperatures to construct accurate modelConclusionAt actual HL-LHC dose-rate (9 Gy/hr) & temp (-15o) the effect will be negligible (pessimistic assumptions)~1.3% max. increase in module power consumptionCERNX-rayfacilityCBC3FC7 readoutIonizing Radiation tests

39. 39wafer probe results83%87%89%81%85%89%84%87%****** 5 wafers to PacTech for bump-bond processinghigh average yield ~85%