DAC38RF82EVM is configured in CMODE3 Jumper JP10 is open Enable OnChip PLL Clock Mode Provided a 4dBm external reference clock250MHz to SMA J4 Checked the PLL Enable box and enter the desired onchip PLL reference clock frequency ID: 1031226
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1. Issue with DCLK divider=1 for CLKout0 and 1 (FPGA clock and SYSREF)DAC38RF82EVM is configured in CMODE3. Jumper JP10 is open (Enable On-Chip PLL Clock Mode).Provided a 4dBm external reference clock=250MHz to SMA J4.Checked the PLL Enable box and enter the desired on-chip PLL reference clock frequency.
2. GUI Front page
3. We are changing DCLK Divider (CLKout 0 and 1) in LMK04828.
4. DCLK Divider=1 Input PLL ref clock is 250MHz and Output frequency is not 250MHz for this case.
5. DCLK Divider=2 Input PLL ref clock is 250MHz and Output frequency is 125MHz for this case
6. DCLK Divider=3 Input PLL ref clock is 250MHz and Output frequency is 83.33MHz for this case
7. DCLK Divider=4 Input PLL ref clock is 250MHz and Output frequency is 62.5MHz for this case
8. DCLK Divider=5 Input PLL ref clock is 250MHz and Output frequency is 50MHz for this case
9. DCLK Divider=2 Input PLL ref clock is 500MHz and Output frequency is 250MHz for this case