Arithmetic Circuits Montek Singh Oct 22 2014 Today s Topics Adder circuits ripplecarry adder revisited more advanced carry lookahead adder Subtraction by adding the negative ID: 201629
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COMP541Arithmetic Circuits
Montek Singh
Oct 22, 2014Slide2
Today’s TopicsAdder circuitsripple-carry adder (revisited)more advanced: carry-lookahead adderSubtractionby adding the negativeOverflow
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Iterative CircuitLike a hierarchy, except functional blocks per bit
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AddersGreat example of this type of designDesign 1-bit circuit, then expandLet’s look atHalf adder – 2-bit adder, no carry inInputs are bits to be addedOutputs: result and possible carryFull adder – includes carry in, really a 3-bit adderWe have already studied adder in Lab 3/Comp411here we look at it from a different anglemodify it to be faster
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Half AdderProduces carry outdoes not handle carry in
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Figure 5.1 1-bit half adderSlide6
Full AdderThree inputsthird is carry inTwo outputssum and carry out
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Two Half Adders (and an OR)
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Ripple-Carry AdderStraightforward – connect full addersCarry-out to carry-in chainCin in case this is part of larger chain, or just ‘0’
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Figure 5.5 32-bit ripple-carry adderSlide9
Lab 3: Hierarchical 4-Bit AdderWe used hierarchy in Lab 3Design full adderUsed 4 of them to make a 4-bit adderUsed 2 4-bit adders to make an 8-bit adder…
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Specifying Addition in Behavioral Verilog// 4-bit Adder: Behavioral Verilogmodule adder_4_b_v(A, B, C0, S, C4); input[3:0] A, B; input C0; output[3:0] S; output C4; assign {C4, S} = A + B + C0;
endmodule
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Addition (unsigned)
Concatenation operationSlide11
What’s the problem with this design?DelayApprox how much?Imagine a 64-bit adderLook at carry chain
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Delays (after assigning delays to gates)Delays are generally higher for more significant bits
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Multibit AddersSeveral types of carry propagate adders (CPAs) are:Ripple-carry adders (slow)Carry-lookahead adders (fast)Prefix adders (faster)
Carry-lookahead and prefix adders are faster for large adders but require more hardware.Adder symbol (right) Slide14
Carry Lookahead AdderNote that add itself just 2 levelsum is produced with a delay of only two XOR gatescarry takes three gates, thoughIdea is to separate carry from adder functionthen make carry fasteractually, we will make carry have a 2-gate delay total, for all the bits of the adder!these two gates might be huge though
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Four-bit Ripple Carry
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Adder function
separated from
carry
Notice adder has A, B, C in
and S out, as well as G,P out.
ReferenceSlide16
PropagateThe P signal is called propagateP = A BMeans to propagate incoming carry
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GenerateThe G is generateG = AB, so new carry createdSo it’s ORed with incoming carry
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Said DifferentlyIf A B and there’s incoming carry, carry will be propagatedAnd S will be 0, of courseIf AB, then will create carryIncoming will determine whether S is 0 or 1
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Ripple Carry Delay: 8 GatesKey observation:G and P are produced by each adder stagewithout needing carry from the right!need only 2 gate delays for all G’s and P’s to be generated!critical path is the carry logic at the bottomthe G’s and P’s are “off the critical path”
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Turn Into Two Gate DelaysRefactor the logicchanged from deep (in delay) to widefor each stage, gather and squish together all the logic to the right
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C1 Just Like Ripple Carry
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C2 Circuit Two Levels
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G from before and P to pass on
This checks two propagates and a carry in Slide23
C3 Circuit Two Levels
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G from before and P to pass on
This checks three propagates and a carry in
Generate from level 0 and two propagates Slide24
What Happens as Scale Up?Can I realistically make 64-bit adder like this?Have to AND 63 propagates and Cin!CompromiseHierarchical designMore levels of gatesuse a tree of AND’sdelay grows only logarithmically
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Making 4-Bit Adder ModuleCreate propagate and generate signals for whole module
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Group PropagateMake propagate of whole 4-bit blockP0-3 = P3P2P1P0
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Group GenerateIndicates carry generated within this block
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Hierarchical Carry
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4-bit adder
A
B
S
G
P
C
in
4-bit adder
A
B
S
G
P
C
in
C
0
Look Ahead
C
8
C
4
Left
lookahead
block is exercise for youSlide29
Practical MattersFPGAs like ours have limited inputs per gateInstead they have special circuits to make addersSo don’t expect to see same results as theory would suggest
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Other Adder CircuitsWhat if hierarchical lookahead too slowOther styles existPrefix adder (explained in text) had a tree to computer generate and propagatePipelined arithmetic units – multicycle but enable faster clock speedThese are for self-study
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Adder-SubtractorNeed only adder and complementer for input to subtractNeed selective complementer to make negative output back from 2’s complement
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Design of Adder/Subtractor
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’
s complement if B > A
Inverts each bit of B if S is 1
Adds 1 to make 2
’
s complement
S low for add,
high for subtractSlide33
OverflowTwo cases of overflow for addition of signed numbersTwo large positive numbers overflow into sign bitNot enough room for resultTwo large negative numbers addedSame – not enough bitsCarry out by itself doesn’t indicate overflow
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Overflow Examples4-bit signed numbers: Sometimes a leftmost carry is generated without overflow:-7 + 75 + (-3)Sometimes a leftmost carry is not generated, but overflow occurs:4 + 4
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Overflow DetectionBasic condition:if two +ve numbers are added and sum is –veif two -ve numbers are added and sum is +veCan be simplified to the following check:either Cn-1 or Cn is high, but not both
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SummaryTodayadders and subtractorsoverflowNext class:full processor datapath
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