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MIPSProgrammersReferenceManualBenRobertsComputerLaboratoryUniversityof


MIPS1IntroductionTheMIPSisa32-bitembeddedsoftcoreprocessorwithavestagepipelineandaRISCinstructionsetTheinitialversionRhinowasdesignedbyRobinMessageandDavidSimnerduringtheirinternshipintheSummer2006Tig

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Document on Subject : "MIPSProgrammersReferenceManualBenRobertsComputerLaboratoryUniversityof"— Transcript:

1 MIPSProgrammer'sReferenceManualBenRobert
MIPSProgrammer'sReferenceManualBenRobertsComputerLaboratoryUniversityofCambridgeJuly2007Sponsoredby: MIPS1IntroductionTheMIPSisa32-bitembeddedsoftcoreprocessorwithavestagepipelineandaRISCinstructionset.Theinitialversion,Rhino,wasdesignedbyRobinMessageandDavidSimnerduringtheirinternshipintheSummer2006.TigerisanupgradedversionofRhino,designedbyBenRobertsandGregoryChadwick.ItisdesignedtobeusedwithAltera'sAvalonbus.The5stagepipelinehasthe”standard”RISCstructure:InstructionFetch!Decode!Execute!MemoryAccess!Writeback2Overview2.1RegistersTheMIPSprocessorhas3232-bitregisters.Theirnames,numbers,uses,andwhetherthecalleemustpreservethemacrossafunctioncallaredetailedinthetablebelow: Name Num

2 ber Use Calleemustpreserve $zero $0 cons
ber Use Calleemustpreserve $zero $0 constant0 N/A $at $1 assemblytemporary no $v0-$v1 $2-$3 functionreturns no $a0-$a3 $4-$7 functionarguments no $t0-$t7 $8-$15 temporaries no $s0-$s7 $16-$23 savedtemporaries yes $t8-$t9 $24-$25 temporaries no $k0-$k1 $26-$27 kerneluse no $gp $28 globalpointer yes $sp $29 stackpointer yes $fp $30 framepointer yes $ra $31 returnaddress N/A TheMIPSalsohastwospecial-purpose32-bitregisters,HIandLO.Theseareusedtostoretheresultsofadivisionormultiplication.Amultiplicationof232-bitnumbersleavesthemostsignicant32bitsinHI,andtheleastsignicant32bitsinLO.AdivisionleavesthequotientinLO,andtheremainderinHI.TheinstructionsMFHIandMTHIallowyoutomovevaluesfromHIi

3 ntoaregister,ormoveavaluefromaregisterin
ntoaregister,ormoveavaluefromaregisterintoHIrespectively.SimilarinstructionsexistforLO.2 2.2ProgramFlowThereare10branchinstructions:BEQ,BNE,BLEZ,BGEZ,BLTZ,BGTZ,J,JAL,JRandJALR.Theseallupdatethepc.TheMIPSmakesuseofabranchdelayslottoremovetheneedtoushthepipelinewhenabranchistaken.Inotherwords,theinstructionimmediatelyfollowingabranchwillalwaysbeexecutedregardlessofwhetherthebranchistakenornot.Ifalinkoperationisspecied,thereturnaddressisstoredin$ra,sojr$rawillreturnfromafunction.Notethatthereturnaddresswillpointtotheinstructionafterthedelayslot,sothatnoinstructionsareexecutedtwice.Forexample,inthecodebelow,8willbemovedto$4beforethejumptothreetakesplace.Also,4willbemovedto$1beforeth

4 epcpointsto”two”.one:addi$2,$0,4#loadcon
epcpointsto”two”.one:addi$2,$0,4#loadconstant4into$2jalthree#jumpto"three"addi$4,$0,8#loadconstant8into$4two:addi$4,$0,6#loadconstant6into$4addi$9,$0,7#loadconstant7into$9jend#jumpto"end"nop#no-opthree:jr$ra#jumptoaddressin$raaddi$1,4#loadconstant4into$1end:nop#nooperation2.3MemoryAccessMemoryaccessisvia.Altera'sAvalonbus.Transfersmayonlytakeplacewhenthebusisready;thismeansthattheprocessormayhavetowaitindenitely.3 2.4InstructionFormatrsIndexofrstoperandregisterrtIndexofsecondoperandregisterrdIndexofdestinationregistershamtShiftamount,usedonlyinshiftoperationsimm16-bitsignedimmediateaddrMemoryaddressR-typeinstruction 31:26 25:21 20:16 15:11 10:6 5:0 opcode rs rt rd shamt funct I-

5 typeinstruction 31:26 25:21 20:16 15:0 o
typeinstruction 31:26 25:21 20:16 15:0 opcode rs rt imm J-typeinstruction 31:26 25:0 opcode addr 4 3InstructionSetQuickReferenceSignImmSign-extendedimmediateconstant=ff16fimm[15]gg,immgZeroImmZero-extendedimmediateconstant=ff16f1'b0gg,immg[addr]Contentsstoredataddressaddr MIPSinstructionset-sortedbyopcode Opcode Mnemonic Operands Function 000000 R-type rsrtrdshamt various-seenexttable 000001 BLTZ($rt=0) rsrtimm if($rs0)PC=BTA BGEZ($rt=1) if($rs0)PC=BTA 000010 J addr PC=addr 000011 JAL addr $ra=PC+4;PC=addr 000100 BEQ rsrtimm if($rs==$rt)PC=BTA 000101 BNE rsrtimm if($rs!=$rt)PC=BTA 000110 BLEZ rsrtimm if($rs0)PC=BTA 000111 BGTZ rsrtimm if($rs�0)PC=BTA 001000 ADDI rsrtimm $

6 rt=$rs+SignImm 001001 ADDIU rsrtimm $rt=
rt=$rs+SignImm 001001 ADDIU rsrtimm $rt=$rs+SignImm 001010 SLTI rsrtimm $rsSignImm?$rt=1:$rt=0 001011 SLTIU rsrtimm $rsSignImm?$rt=1:$rt=0 001100 ANDI rsrtimm $rt=$rs&ZeroImm 001101 ORI rsrtimm $rt=$rsjZeroImm 001110 XORI rsrtimm $rt=$rsZeroImm 001111 LUI rsrtimm $rt=fimm,f16f1'b0ggg 100000 LB rsrtimm $rt=ff24f[addr][7]gg,[addr][7:0]g 100001 LH rsrtimm $rt=ff16f[addr][15]gg,[addr][15:0]g 100011 LW rsrtimm $rt=[addr] 100100 LBU rsrtimm $rt=ff24f1'b0gg,[addr][7:0]g 100101 LHU rsrtimm $rt=ff16f1'b0gg,[addr][15:0]g 101000 SB rsrtimm [addr][7:0]=$rt[7:0] 101001 SH rsrtimm [addr][15:0]=$rt[15:0] 101011 SW rsrtimm [addr]=$rt 010000 MFC0($rs=0) rdrt $rt=$rd MTC0($rs=4) rdrt $rd=$rt ($rdi

7 sincoprocessor0) 5 R-typeinstructions-so
sincoprocessor0) 5 R-typeinstructions-sortedbyfunct allhaveoperandsrs,rt,rdandshamt Funct Mnemonic Operation 000000 SLL $rd=$rtshamt 000001 SRL $rd=$rt��shamt 000011 SRA $rd=$rt���shamt 000100 SLLV $rd=$rt$rs[4:0] assembly:sllvrdrtrs 000110 SRLV $rd=$rt��$rs[4:0] assembly:srlvrdrtrs 000111 SRAV $rd=$rt���$rs[4:0] assembly:sravrdrtrs 001000 JR PC=$rs 001001 JALR $ra=PC+4;PC=$rs 010000 MFHI $rd=$hi 010001 MTHI $hi=$rs 010010 MFLO $rd=$lo 010011 MTLO $lo=$rs 011000 MULT f$hi,$log=($rs$rt) 011001 MULTU f$hi,$log=($rs$rt) 011010 DIV $lo=$rs/$rt $hi=$rs%$rt 011011 DIVU $lo=$rs/$rt $hi=$rs%$rt 100000 ADD $rd=$rs+$rt

8 100001 ADDU $rd=$rs+$rt 100010 SUB $rd=$
100001 ADDU $rd=$rs+$rt 100010 SUB $rd=$rs$rt 100011 SUBU $rd=$rs$rt 100100 AND $rd=$rs&$rt 100101 OR $rd=$rsj$rt 100110 XOR $rd=$rs$rt 100111 NOR $rd=:($rsj$rt) 101010 SLT $rs$rt?$rd=1:$rd=0 101011 SLTU $rs$rt?$rd=1:$rd=0 6 ADDADDRegisterSignedType:R-TypeOperation:$rd=$rs+$rtAssemblerSyntax:addrdrsrtExample:add$s0,$s1,$s2Description:Addthevaluescontainedinregisters$rsand$rtandplacetheresultin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100000 ADDUADDRegisterUnsignedType:R-TypeOperation:$rd=$rs+$rtAssemblerSyntax:addurdrsrtExample:addu$s0,$s1,$s2Description:Addthevaluescontainedinregisters$rs

9 and$rtandplacetheresultin$rdInstructionF
and$rtandplacetheresultin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100001 7 ADDIADDImmediateSignedType:I-TypeOperation:$rt=$rs+ff16fimm[15]gg,immgAssemblerSyntax:addirtrsimmExample:addi$s0,$s1,5Description:Addthevaluecontainedinregister$rstotheimmediateconstantandplacetheresultin$rtInstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001000 rs rt imm ADDIUADDImmediateUnsignedType:I-TypeOperation:$rd=$rs+ff16fimm[15]gg,immgAssemblerSyntax:addiurtrsimmExample:addiu$s0,$s1,5Description:Addthevaluecontainedinregister$rstotheimmediateconstantandplaceth

10 eresultin$rtInstructionFields:Sourceregi
eresultin$rtInstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001001 rs rt imm 8 ANDBitwiseRegisterANDType:R-TypeOperation:$rd=$rs&$rtAssemblerSyntax:andrdrsrtExample:and$s0,$s1,$s2Description:BitwiseANDthecontentsofregisters$rsand$rtandplacetheresultin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100100 ANDIBitwiseImmediateANDType:I-TypeOperation:$rt=$rs&ff16f1'b0gg,immgAssemblerSyntax:andirdrsrtExample:andi$s0,$s1,$s2Description:BitwiseANDthecontentsofregister$rswiththeimmediatecon-stantzero-extendedto32-bitsandplacetheresultin$rtInstructionField

11 s:SourceregisterrsImmediateconstantimmDe
s:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001100 rs rt imm 9 BEQBranchifEqualType:I-TypeOperation:if($rs==$rt)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:beqrsrtaddrExample:beq$s0,$s1,lblDescription:Ifthecontentsofregisters$rsand$rtareequal,thenbranchtoaddr;otherwisecontinuesequentialexecution.Theinstructionsequen-tiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:Sourceregister1rsSourceregister2rtDestinationaddressaddr 31:26 25:21 20:16 15:0 000100 rs rt addr BNEBranchifNotEqualType:I-TypeOperation:if($rs!=$rt)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:bnersrtaddrExample:bne$s0,$s1,lblDescripti

12 on:Ifthecontentsofregisters$rsand$rtaren
on:Ifthecontentsofregisters$rsand$rtarenotequal,thenbranchtoaddr;otherwisecontinuesequentialexecution.Theinstructionse-quentiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:Sourceregister1rsSourceregister2rtDestinationaddressaddr 31:26 25:21 20:16 15:0 000100 rs rt addr 10 BGEZBranchifGreaterThanorEqualtoZeroType:I-TypeOperation:if($rs0)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:bgezrsaddrExample:bgez$s0,lblDescription:Ifthecontentsofregister$rsis0,thenbranchtoaddr;otherwisecontinuesequentialexecution.Theinstructionsequentiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:SourceregisterrsDestinationaddressaddr

13 31:26 25:21 20:16 15:0 000001 rs 00001
31:26 25:21 20:16 15:0 000001 rs 00001 addr BGTZBranchifGreaterThanZeroType:I-TypeOperation:if($rs�0)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:bgtzrsaddrExample:bgtz$s0,lblDescription:Ifthecontentsofregister$rsis�0,thenbranchtoaddr;otherwisecontinuesequentialexecution.Theinstructionsequentiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:SourceregisterrsDestinationaddressaddr 31:26 25:21 20:16 15:0 000111 rs xxxxx addr 11 BLEZBranchifLessThanorEqualtoZeroType:I-TypeOperation:if($rs0)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:blezrsaddrExample:blez$s0,lblDescription:Ifthecontentsofregister$rsis0,thenbranchtoaddr;other

14 wisecontinuesequentialexecution.Theinstr
wisecontinuesequentialexecution.Theinstructionsequentiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:SourceregisterrsDestinationaddressaddr 31:26 25:21 20:16 15:0 000110 rs xxxxx addr BLTZBranchifLessThanZeroType:I-TypeOperation:if($rs0)PC=PC+4+ff14faddr[15]gg,addr,2'b00gAssemblerSyntax:bltzrsaddrExample:bltz$s0,lblDescription:Ifthecontentsofregister$rsis0,thenbranchtoaddr;otherwisecontinuesequentialexecution.Theinstructionsequentiallyafterthebranchwillalwaysbeexecutedduetothebranchdelayslot.InstructionFields:SourceregisterrsDestinationaddressaddr 31:26 25:21 20:16 15:0 000001 rs 00000 addr 12 DIVSignedRegisterDivideType:R-TypeOperation:$lo=$rs/$rt

15 $hi=$rs%$rtAssemblerSyntax:divrsrtExampl
$hi=$rs%$rtAssemblerSyntax:divrsrtExample:div$s0,$s1Description:Compute$rs$rt,storethequotientin$loandtheremainderin$hiInstructionFields:Sourceregister1rsSourceregister2rt 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt xxxxx 00000 011010 DIVUUnsignedRegisterDivideType:R-TypeOperation:$lo=$rs/$rt$hi=$rs%$rtAssemblerSyntax:divursrtExample:divu$s0,$s1Description:Compute$rs$rt,storethequotientin$loandtheremainderin$hi.Treats$rsand$rtasunsignedintegersInstructionFields:Sourceregister1rsSourceregister2rt 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt xxxxx 00000 011011 13 JUnconditionalJumpType:J-TypeOperation:PC=f(PC+4)[31:28],addr,2'b00gAssemblerSyntax:jaddrExample:jlblDescription:Jum

16 prelativetothecurrentPCby(addr2)Instruct
prelativetothecurrentPCby(addr2)InstructionFields:Addressaddr 31:26 25:0 000010 addr JALUnconditionalJumpandLinkType:J-TypeOperation:$ra=PC+4;PC=f(PC+4)[31:28],addr,2'b00gAssemblerSyntax:jaladdrExample:jallblDescription:StorePC+4in$ra,thenjumprelativetothecurrentPCby(addr2)InstructionFields:Addressaddr 31:26 25:0 000011 addr 14 JRUnconditionalRegisterJumpType:R-TypeOperation:PC=$rsAssemblerSyntax:jr$rsExample:jr$raDescription:Jumptoaddressstoredin$rsInstructionFields:Sourceregisterrs 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs xxxxx xxxxx 00000 001000 JALRUnconditionalRegisterJumpandLinkType:R-TypeOperation:$ra=PC+4;PC=$rsAssemblerSyntax:jalr$rsExample:jalr$s0Description:StorePC+4i

17 n$rathenjumptoaddressstoredin$rsInstruct
n$rathenjumptoaddressstoredin$rsInstructionFields:Sourceregisterrs 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs xxxxx xxxxx 00000 001001 15 LBLoadByteType:I-TypeOperation:$rt=ff24f[Address][7]gg,[Address][7:0]gAddress=$rs+ff16fimm[15]gg,immgAssemblerSyntax:lbrtimm(rs)Example:lb$s020($s1)Description:Loadsign-extendedlowerbyteofmemorycontentsataddress$rsoffsetbyimminto$rtInstructionFields:RegistercontainingbaseaddressrsOffsetimmDestinationregisterrt 31:26 25:21 20:16 15:0 100000 rs rt imm LBULoadByteUnsignedType:I-TypeOperation:$rt=ff24f1'b0gg,[Address][7:0]gAddress=$rs+ff16fimm[15]gg,immgAssemblerSyntax:lburt,imm(rs)Example:lbu$s020($s1)Description:Loadzero-extendedlowerbyteofmemoryc

18 ontentsataddress$rsoffsetbyimminto$rtIns
ontentsataddress$rsoffsetbyimminto$rtInstructionFields:RegistercontainingbaseaddressrsOffsetimmDestinationregisterrt 31:26 25:21 20:16 15:0 100100 rs rt imm 16 LHLoadHalfwordType:I-TypeOperation:$rt=ff16f[Address][15]gg,[Address][15:0]gAddress=$rs+ff16fimm[15]gg,immgAssemblerSyntax:lhrtimm(rs)Example:lh$s0,20($s1)Description:Loadsign-extendedlower2bytesofmemorycontentsataddress$rsoffsetbyimminto$rtInstructionFields:RegistercontainingbaseaddressrsOffsetimmDestinationregisterrt 31:26 25:21 20:16 15:0 100001 rs rt imm LHULoadHalfwordUnsignedType:I-TypeOperation:$rt=ff16f1'b0gg,[Address][15:0]gAddress=$rs+ff16fimm[15]gg,immgAssemblerSyntax:lhurtimm(rs)Example:lhu$s0,20($s1)Description

19 :Loadzero-extendedlower2bytesofmemorycon
:Loadzero-extendedlower2bytesofmemorycontentsataddress$rsoffsetbyimminto$rtInstructionFields:RegistercontainingbaseaddressrsOffsetimmDestinationregisterrt 31:26 25:21 20:16 15:0 100101 rs rt imm 17 LWLoadWordType:I-TypeOperation:$rt=[Address]Address=$rs+ff16fimm[15]gg,immgAssemblerSyntax:lwrtimm(rs)Example:lw$s0,20($s1)Description:Loadmemorycontentsataddress$rsoffsetbyimminto$rtInstructionFields:RegistercontainingbaseaddressrsOffsetimmDestinationregisterrt 31:26 25:21 20:16 15:0 100011 rs rt imm LUILoadUpperImmediateType:I-TypeOperation:$rt=fimm,f16f1'b0gggAssemblerSyntax:luirtimmExample:luirt,9Description:Load16-bitimmediateconstantintoupper16bitsofregister$rtInstructionFields:I

20 mmediateconstantimmDestinationregisterrt
mmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001111 xxxxx rt imm 18 MFHIMoveFromHIType:R-TypeOperation:$rd=$hiAssemblerSyntax:mfhirdExample:mfhi$s0Description:Copyvalueinregister$hiintoregister$rdInstructionFields:Destinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 xxxxx xxxxx rd 00000 010000 MTHIMoveToHIType:R-TypeOperation:$hi=$rsAssemblerSyntax:mthirsExample:mthi$s2Description:Copyvalueinregister$rsintoregister$hiInstructionFields:Sourceregisterrs 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs xxxxx xxxxx 00000 010001 19 MFLOMoveFromLOType:R-TypeOperation:$rd=$loAssemblerSyntax:mordExample:mflo$s0Description:Copyvalueinregister$lointoregister$rdInstruc

21 tionFields:Destinationregisterrd 31:26 2
tionFields:Destinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 xxxxx xxxxx rd 00000 010010 MTLOMoveToLOType:R-TypeOperation:$lo=$rsAssemblerSyntax:mtlorsExample:mtlo$s2Description:Copyvalueinregister$rsintoregister$loInstructionFields:Sourceregisterrs 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs xxxxx xxxxx 00000 010011 20 MFC0MoveFromCoprocessor0Type:R-TypeOperation:$rt=$rd$rdisincoprocessor0AssemblerSyntax:mfc0rtrdExample:mfc0$t0$statusDescription:Copyvalueincoprocessorregister$rdintoregister$rtSeetheprocessorinternalsguideforfurtherinformation.InstructionFields:DestinationregisterrtCoprocessorsourceregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 010000 00000 rt rd 00000 000

22 000 MTC0MoveToCoprocessor0Type:R-TypeOpe
000 MTC0MoveToCoprocessor0Type:R-TypeOperation:$rd=$rt$rdisincoprocessor0AssemblerSyntax:mtc0rtrdExample:mtc0$t0$statusDescription:Copyvalueinregister$rtintocoprocessorregister$rdSeetheprocessorinternalsguideforfurtherinformation.InstructionFields:SourceregisterrtCoprocessordestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 010000 00100 rt rd 00000 000000 21 MULTSignedRegisterMultiplyType:R-TypeOperation:f$hi,$log=($rs$rt)AssemblerSyntax:multrsrtExample:mult$s0,$s1Description:Multiplythecontentsinregister$rsbythecontentsin$rt,storetheupper4bytesin$hi,andthelower4bytesin$loInstructionFields:Sourceregister1rsSourceregister2rt 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt xxxxx

23 00000 011000 MULTUUnsignedRegisterMultip
00000 011000 MULTUUnsignedRegisterMultiplyType:R-TypeOperation:f$hi,$log=($rs$rt)AssemblerSyntax:multursrtExample:multu$s0,$s1Description:Multiplythecontentsinregister$rsbythecontentsin$rt,storetheupper4bytesin$hi,andthelower4bytesin$lo.Treatsregistercontentsasunsignednumbers.InstructionFields:Sourceregister1rsSourceregister2rt 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt xxxxx 00000 011001 22 MULSignedRegisterMultiplywithoutHIorLOType:R-TypeOperation:$rd=($rs$rt)[31:0]AssemblerSyntax:mulrdrsrtExample:mul$s0,$s1,$s2Description:Multiplythecontentsinregister$rsbythecontentsin$rt,storethelower4bytesin$rd.Theupper4bytesarediscarded.InstructionFields:Sourceregister1rsSourceregister2

24 rtDestinationregisterrd 31:26 25:21 20:1
rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 011100 rs rt rd 00000 000010 23 NOPNo-operationType:R-TypeOperation:NoneAssemblerSyntax:nopExample:nopDescription:Doesnothing.Equivalenttoor$s0$s0$s0InstructionFields:none 31:26 25:21 20:16 15:11 10:6 5:0 000000 00000 00000 00000 00000 000000 NORBitwiseRegisterNORType:R-TypeOperation:$rd=($rsj$rt)AssemblerSyntax:norrdrsrtExample:nor$s0,$s1,$s2Description:PerformsthebitwiseORofthecontentsofregisters$rsand$rt,negatestheanswerandstoresthisin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100111 24 ORBitwiseRegisterORType:R-TypeOperation:$rd=$rsj

25 $rtAssemblerSyntax:orrdrsrtExample:or$s0
$rtAssemblerSyntax:orrdrsrtExample:or$s0,$s1,$s2Description:PerformsthebitwiseORofthecontentsofregisters$rsand$rt,andstorestheanswerin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100101 ORIBitwiseImmediateORType:I-TypeOperation:$rd=$rtjff16f1'b0gg,immgAssemblerSyntax:orirtrsimmExample:ori$s0,$s1,-5Description:PerformsthebitwiseORofthecontentoftheregister$rswiththezero-extendedimmediateconstantandstorestheanswerin$rtInstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001101 rs rt imm 25 SBStoreByteType:I-TypeOperation:[Address][7:0]=$rt[7:0]Address=$

26 rs+ff16fimm[15]gg,immgAssemblerSyntax:sb
rs+ff16fimm[15]gg,immgAssemblerSyntax:sbrtimm(rs)Example:sb$s0,20($s1)Description:Storesthelower8bitsin$rtintothelower8bitsofthememorylocationat$rsoffsetbythesign-extendedimmediateconstant.InstructionFields:BaseaddressregisterrsImmediateconstantimmSourceRegisterrt 31:26 25:21 20:16 15:0 101000 rs rt imm SHStoreHalfwordType:I-TypeOperation:[Address][15:0]=$rt[15:0]Address=$rs+ff16fimm[15]gg,immgAssemblerSyntax:shrtimm(rs)Example:sh$s0,20($s1)Description:Storesthelower16bitsin$rtintothelower16bitsofthememorylocationat$rsoffsetbythesign-extendedimmediateconstant.InstructionFields:BaseaddressregisterrsImmediateconstantimmSourceRegisterrt 31:26 25:21 20:16 15:0 101001 rs rt imm 26 SWSt

27 oreWordType:I-TypeOperation:[Address]=$r
oreWordType:I-TypeOperation:[Address]=$rtAddress=$rs+ff16fimm[15]gg,immgAssemblerSyntax:swrtimm(rs)Example:sw$s0,20($s1)Description:Storesthecontentsofregister$rtintothememorylocationat$rsoffsetbythesign-extendedimmediateconstant.InstructionFields:BaseaddressregisterrsImmediateconstantimmSourceRegisterrt 31:26 25:21 20:16 15:0 101011 rs rt imm 27 SLLShiftLeftLogicalType:R-TypeOperation:$rd=$rtshamtAssemblerSyntax:sllrdrtshamtExample:sll$s0,$s1,2Description:Leftshiftsthecontentsofregister$rtbyshamt,paddingwithzeros.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountshamtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 xxxxx rt rd shamt 000000 SLLVShiftL

28 eftLogicalVariableType:R-TypeOperation:$
eftLogicalVariableType:R-TypeOperation:$rd=$rt$rs[4:0]AssemblerSyntax:sllvrdrtrsNotethechangeinordertonormalR-TypeinstructionsExample:sllv$s0,$s1,$s2Description:Leftshiftsthecontentsofregister$rtbytheamountstoredinthelower4bitofregister$rs,paddingwithzeros.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountregisterrsDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 000100 28 SRLShiftRightLogicalType:R-TypeOperation:$rd=$rt��shamtAssemblerSyntax:srlrdrtshamtExample:srl$s0,$s1,2Description:Rightshiftsthecontentsofregister$rtbyshamt,paddingwithzeros.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountshamtDestina

29 tionregisterrd 31:26 25:21 20:16 15:11 1
tionregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 xxxxx rt rd shamt 000010 SRLVShiftRightLogicalVariableType:R-TypeOperation:$rd=$rt��$rs[4:0]AssemblerSyntax:srlvrdrtrsNotethechangeinordertonormalR-TypeinstructionsExample:srlv$s0,$s1,$s2Description:Rightshiftsthecontentsofregister$rtbytheamountstoredinthelower4bitofregister$rs,paddingwithzeros.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountregisterrsDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 000100 29 SRAShiftRightArithmeticType:R-TypeOperation:$rd=$rt���shamtAssemblerSyntax:srardrtshamtExample:sra$s0,$s1,2Description:Rightshiftstheconten

30 tsofregister$rtbyshamt,paddingwithacopyo
tsofregister$rtbyshamt,paddingwithacopyof$rt[31]i.e.asign-preservingshift.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountshamtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 xxxxx rt rd shamt 000011 SRAVShiftRightArithmeticVariableType:R-TypeOperation:$rd=$rt���$rs[4:0]AssemblerSyntax:sravrdrtrsNotethechangeinordertonormalR-TypeinstructionsExample:srav$s0,$s1,$s2Description:Rightshiftsthecontentsofregister$rtbytheamountstoredinthelower4bitofregister$rs,paddingwithacopyof$rt[31]i.e.asign-preservingshift.Theresultisstoredin$rdInstructionFields:SourceregisterrtShiftamountregisterrsDestinationregisterrd 31:26 25:21 20:16 15:11 10:

31 6 5:0 000000 rs rt rd 00000 000111 30 SL
6 5:0 000000 rs rt rd 00000 000111 30 SLTSetLessThanRegisterType:R-TypeOperation:$rs$rt?$rd=1:$rd=0AssemblerSyntax:sltrdrsrtExample:slt$s0,$s1,$s2Description:If$rsˇ$rtthen$rdissetto0,otherwiseitissetto1.InstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 101010 SLTUSetLessThanUnsignedRegisterType:R-TypeOperation:$rs$rt?$rd=1:$rd=0AssemblerSyntax:slturdrsrtExample:sltu$s0,$s1,$s2Description:If$rsˇ$rtthen$rdissetto0,otherwiseitissetto1.Treatsoperandsasunsignednumbers.InstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 101011 31 SLT

32 ISetLessThanImmediateType:I-TypeOperatio
ISetLessThanImmediateType:I-TypeOperation:$rsff16fimm[15]gg,immg?$rt=1:$rt=0AssemblerSyntax:sltirtrsimmExample:slti$s0,$s1,9Description:If$rsˇ(sign-extendedimmediateconstant)then$rtissetto0,other-wiseitissetto1.InstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001010 rs rt imm SLTIUSetLessThanUnsignedImmediateType:I-TypeOperation:$rsff16fimm[15]gg,immg?$rt=1:$rt=0AssemblerSyntax:sltiurtrsimmExample:sltiu$s0,$s1,9Description:If$rsˇ(sign-extendedimmediateconstant)then$rdissetto0,oth-erwiseitissetto1.Treatsoperandasunsignednumbers.InstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001011

33 rs rt imm 32 SUBSUBRegisterSignedType:R-
rs rt imm 32 SUBSUBRegisterSignedType:R-TypeOperation:$rd=$rs$rtAssemblerSyntax:subrdrsrtExample:sub$s0,$s1,$s2Description:Subtractthevaluecontainedinregister$rtfromthevaluecontainedinregister$rsandplacetheresultin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100010 SUBUSUBRegisterUnsignedType:R-TypeOperation:$rd=$rs$rtAssemblerSyntax:suburdrsrtExample:subu$s0,$s1,$s2Description:Subtractthevaluecontainedinregister$rtfromthevaluecontainedinregister$rsandplacetheresultin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00

34 000 100011 33 XORBitwiseRegisterXORType:
000 100011 33 XORBitwiseRegisterXORType:R-TypeOperation:$rd=$rs$rtAssemblerSyntax:xorrdrsrtExample:xor$s0,$s1,$s2Description:PerformsthebitwiseXORofthecontentsofregisters$rsand$rt,andstorestheanswerin$rdInstructionFields:Sourceregister1rsSourceregister2rtDestinationregisterrd 31:26 25:21 20:16 15:11 10:6 5:0 000000 rs rt rd 00000 100110 XORIBitwiseImmediateXORType:I-TypeOperation:$rd=$rtff16f1'b0gg,immgAssemblerSyntax:xorirtrsimmExample:xori$s0,$s1,-5Description:PerformsthebitwiseXORofthecontentoftheregister$rswiththezero-extendedimmediateconstantandstorestheanswerin$rtInstructionFields:SourceregisterrsImmediateconstantimmDestinationregisterrt 31:26 25:21 20:16 15:0 001110 rs rt