HGTD TESTBENCH ZC706 + SIMPLE FMC BOARD HGTD
Description: HGTD TESTBENCH ZC706 SIMPLE FMC BOARD HGTD TESTBENCH ZC706 SIMPLE FMC BOARD ALTIROC2 FIRMWARE BLOCK DIAGRAM ZYNQ AXI INTERC HGTD IP AXI IIC AXI DMA AXI INTERC CONCAT PROCESSOR SYSTEM RESET CLOCK WIZARD POWEENb HARDRSTb PORRSTb
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slide1. HGTD TESTBENCH
ZC706 + SIMPLE FMC BOARD<br>
slide2. HGTD TESTBENCH
ZC706 + SIMPLE FMC BOARD + ALTIROC2<br>
slide3. FIRMWARE BLOCK DIAGRAM ZYNQ AXI
INTERC HGTD
IP AXI IIC AXI DMA AXI
INTERC CONCAT PROCESSOR
SYSTEM RESET CLOCK
WIZARD POWE_ENb
HARD_RSTb
POR_RSTb
EXT_CMD_RSTb
EXT_CMD_L1
EXT_CMD_SETTRIGID
EXT_TRIG1
EXT_TRIG2
EXT_DISC_P/N
PULSE_P/N
TOA_BUSY_P/N LUMI_P/N TIMING_P/N FAST_CMD_P/N I2C SPI ETHERNET 200MHz ZC706 SIMPLE FMC CLK40_P.N<br>
slide4. 4 FMC SIMPLE BOARD - TOP VIEW<br>
slide5. 5 FMC SIMPLE BOARD - BOTTOM VIEW<br>
slide6. The configuration sequence is divided in 8 steps as below :
1. Power on the developement kit ZC706 & Simple FMC board.
2. Power on the mezzanine board by set the bit-0 of CONTROL REGISTER 1
3. Configure ALTEROC asic via the i2c bus. (the i2c slave address is 3).
4. Synchronize the timing lines.
5. Synchronize the luminosity lines.
6. Send a SYNCLUMI command to stop the synchro frame on the fast command lines.
7. Enable DMA
8. Clear the bit-14 and bit-13 of CONTROL REGISTER 1 to enable the timing and luminosity readout. CONFIGURATION SEQUENCE AFTER POWER ON<br>
slide7. 31 0 CONTROL REGISTER 0 (offset 0) Bit-0 : Fast Command GBRST (Global Reset) ® TimeStamp = 0, TrigTag = 0
Bit-1 : Fast Command CAL
Bit-2 : Fast Command SETTRIGID. Immediately after this command 3 TRIGID commands will be sent automatically
Bit-3 : Fast Command TRIGGER. This command is systematically preceded by the SETTRIGID and 3xTRIGID commands. If the Testbeam mode is set,
If the Testbeam mode is enabled, this command will be preceded by a CAL command. The TrigTag will increment by one after this command.
Bit-4 : Fast Command BCR
Bit-5 : Fast Command BCRTRIG
Bit-6 : Fast Command SYNCLUMI
Bit-28:7 : Reserve
Bit-29 : External Command Reset ® Ext_Cmd_Rstb
Bit-30 : Por Reset ® Por_Rstb
Bit-31 : Hard Reset ® Hard_Rstb 31 0 CONTROL REGISTER 1 (offset 1) Bit-0 : Power Enable
Bit-1 : Enable Debug Command CAL
Bit-2 : Enable Debug Command SETTRIGID
Bit-3 : Enable Debug Command L1
Bit-4 : Enable Ext_Trig0
Bit-5 : Enable Ext_Trig1
Bit-6 : Enable Toa_Busy
Bit-12:6 : Reserve
Bit-13 : Disable Luminosity Data
Bit-14 : Disable Timing Data
Bit-15 : Testbeam Mode
Bit-31:16 : Nb IDLE between CAL command and SETTRIGID command 15 16 3 6 7 14 4 29 28 FPGA REGISTERS (AXI_REG) 5 6 13 1 2 3 4 5 1 2 7 12<br>
slide8. SIGNALS
CLK40_P/N & HARD_RSTb CLK40_P/N HARD_RSTb<br>
slide9. SIGNALS
CLK40_P/N & POR_RSTb CLK40_P/N POR_RSTb<br>
slide10. SIGNALS
CLK40_P/N & EXT_CMD_RSTb CLK40_P/N EXT_CMD_RSTb<br>
slide11. SIGNALS
FAST_CMD_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID FAST_CMD_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID<br>
slide12. SIGNALS
FAST_CMD_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID FAST_CMD_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID<br>
slide13. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 1
PULSE SHIFT = 0<br>
slide14. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 1
PULSE SHIFT = 1<br>
slide15. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 2
PULSE SHIFT = 1<br>
slide16. SIGNALS
I2C_2_SCL_FROM_FPGA & I2C_2_SDA_FROM_FPGA I2C_2_SCL I2C_2_SDA<br>
slide17. SIGNALS
I2C_2_SCL_ASIC & I2C_2_SDA_ASIC I2C_2_SCL_ASIC I2C_2_SDA_ASIC<br>
ZC706 + SIMPLE FMC BOARD<br>
slide2. HGTD TESTBENCH
ZC706 + SIMPLE FMC BOARD + ALTIROC2<br>
slide3. FIRMWARE BLOCK DIAGRAM ZYNQ AXI
INTERC HGTD
IP AXI IIC AXI DMA AXI
INTERC CONCAT PROCESSOR
SYSTEM RESET CLOCK
WIZARD POWE_ENb
HARD_RSTb
POR_RSTb
EXT_CMD_RSTb
EXT_CMD_L1
EXT_CMD_SETTRIGID
EXT_TRIG1
EXT_TRIG2
EXT_DISC_P/N
PULSE_P/N
TOA_BUSY_P/N LUMI_P/N TIMING_P/N FAST_CMD_P/N I2C SPI ETHERNET 200MHz ZC706 SIMPLE FMC CLK40_P.N<br>
slide4. 4 FMC SIMPLE BOARD - TOP VIEW<br>
slide5. 5 FMC SIMPLE BOARD - BOTTOM VIEW<br>
slide6. The configuration sequence is divided in 8 steps as below :
1. Power on the developement kit ZC706 & Simple FMC board.
2. Power on the mezzanine board by set the bit-0 of CONTROL REGISTER 1
3. Configure ALTEROC asic via the i2c bus. (the i2c slave address is 3).
4. Synchronize the timing lines.
5. Synchronize the luminosity lines.
6. Send a SYNCLUMI command to stop the synchro frame on the fast command lines.
7. Enable DMA
8. Clear the bit-14 and bit-13 of CONTROL REGISTER 1 to enable the timing and luminosity readout. CONFIGURATION SEQUENCE AFTER POWER ON<br>
slide7. 31 0 CONTROL REGISTER 0 (offset 0) Bit-0 : Fast Command GBRST (Global Reset) ® TimeStamp = 0, TrigTag = 0
Bit-1 : Fast Command CAL
Bit-2 : Fast Command SETTRIGID. Immediately after this command 3 TRIGID commands will be sent automatically
Bit-3 : Fast Command TRIGGER. This command is systematically preceded by the SETTRIGID and 3xTRIGID commands. If the Testbeam mode is set,
If the Testbeam mode is enabled, this command will be preceded by a CAL command. The TrigTag will increment by one after this command.
Bit-4 : Fast Command BCR
Bit-5 : Fast Command BCRTRIG
Bit-6 : Fast Command SYNCLUMI
Bit-28:7 : Reserve
Bit-29 : External Command Reset ® Ext_Cmd_Rstb
Bit-30 : Por Reset ® Por_Rstb
Bit-31 : Hard Reset ® Hard_Rstb 31 0 CONTROL REGISTER 1 (offset 1) Bit-0 : Power Enable
Bit-1 : Enable Debug Command CAL
Bit-2 : Enable Debug Command SETTRIGID
Bit-3 : Enable Debug Command L1
Bit-4 : Enable Ext_Trig0
Bit-5 : Enable Ext_Trig1
Bit-6 : Enable Toa_Busy
Bit-12:6 : Reserve
Bit-13 : Disable Luminosity Data
Bit-14 : Disable Timing Data
Bit-15 : Testbeam Mode
Bit-31:16 : Nb IDLE between CAL command and SETTRIGID command 15 16 3 6 7 14 4 29 28 FPGA REGISTERS (AXI_REG) 5 6 13 1 2 3 4 5 1 2 7 12<br>
slide8. SIGNALS
CLK40_P/N & HARD_RSTb CLK40_P/N HARD_RSTb<br>
slide9. SIGNALS
CLK40_P/N & POR_RSTb CLK40_P/N POR_RSTb<br>
slide10. SIGNALS
CLK40_P/N & EXT_CMD_RSTb CLK40_P/N EXT_CMD_RSTb<br>
slide11. SIGNALS
FAST_CMD_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID FAST_CMD_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID<br>
slide12. SIGNALS
FAST_CMD_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID FAST_CMD_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID<br>
slide13. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 1
PULSE SHIFT = 0<br>
slide14. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 1
PULSE SHIFT = 1<br>
slide15. SIGNALS
PULSE_P/N & EXT_CMD_L1 & EXT_CMD_SETTRIGID PULSE_P/N EXT_CMD_L1 EXT_CMD_SETTRIGID PULSE WIDTH = 2
PULSE SHIFT = 1<br>
slide16. SIGNALS
I2C_2_SCL_FROM_FPGA & I2C_2_SDA_FROM_FPGA I2C_2_SCL I2C_2_SDA<br>
slide17. SIGNALS
I2C_2_SCL_ASIC & I2C_2_SDA_ASIC I2C_2_SCL_ASIC I2C_2_SDA_ASIC<br>