Vaibhav Verma Mandi Das Wole Jaiyeoba Motivation We wanted to build an onchip thermal sensing unit And we wanted to scale voltage and frequency of the processor based on thermal sensor data We will build a beautiful DVFS unit ID: 779169
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Slide1
Dynamic Frequency Scaling using on-chip Thermal Sensors in ASAP7 7nm Predictive PDK
Vaibhav Verma
Mandi Das
Wole Jaiyeoba
Slide2Motivation
We wanted to build an on-chip thermal sensing unit.And we wanted to scale voltage and frequency of the processor based on thermal sensor data.
We will build a beautiful DVFS unit
Well voltage scaling isn’t our cup of tea
Slide3System Block Diagram
Slide4Thermal Sensor (TS)
Clock IN
Temperature Dependent Delay
Temperature Independent Delay
Temperature Dependent Pulse Width
Based on Chen et al., “A Time-to-Digital-Converter-Based CMOS Smart Temperature Sensor”, IEEE Journal Of Solid-State Circuits, Vol. 40, No. 8, August 2005
Slide5Why temperature Independent Delay?Well why not?
Essentially we could have just used wire delay to get the desired temperature dependent pulse width.But that leads to huge “minimum pulse” for lower range of temperatures.
Hence we designed temperature (mostly) invariant delay line to offset the pulse width for better accuracy.And anyway what’s VLSI project without a li’l circuit design!!
Slide6Schematics – Temperature Sensor
Temperature Sensor
Temperature Invariant Delay element
Slide7Performance of TS across temperature
60.9
ps
2.3
ps
Mostly linear across temperature range (-40
°C to 125 °C)
64.3
ps
Slide8Time to Digital Converter (TDC)
The output of thermal sensor is a pulse width varying with temperature.We need TDC to convert this analog information to digital output.
This digital output is then used to control frequency scaling.
Slide9Schematics – Time to Digital Converter
D-Flip Flop
Slide10Why do we need it??
The DFS (Dynamic Frequency Scalar) collects digitalized data from the Time to Digital Converter (DTC) and scales the frequency of the master clock accordingly. This output clock becomes the new clock which drives the chip.
Dynamic Frequency Scalar (DFS)
Slide11Dynamic Frequency Scalar
Features:
**Glitch free** (via use of the two synchronizing flip-flops)
Easily scalable to larger frequency variations.
Based on Browne B. Richard et al., “Low-Latency, HDL-Synthesizable Dynamic Clock Frequency Controller with Self-Referenced Hybrid Clocking”, Circuits and Systems Conference (2006)
Glitch-free dynamic frequency controller.
Final system output clock
Slide12Fig: schematic of the Digital Frequency Scalar
MUX: clock select
DFFs: clock synchronizers
DFFs: clock dividers
System clock
Dynamic Frequency Scalar: Schematic
Fig: DFS Schematic from ASAP7 PDK Cadence
Slide13Using relative ground, we got unexpected results from simulating the design schematic. However, when we connected
Vss and
Vpw to absolute ground, we got the correct, required behavior.
Difficulties encountered during design and simulation
Slide14Fig: simulation of the DFS schematic
DFS – Simulation Waveform Diagram