Unit - II The ARM processor - PowerPoint Presentation

1. Unit - IIThe ARM processor

2. Beagle Bone :Beagle BoardBeagle BoardxMBeagle Bone WhiteBeagle Bone BlackBased on ARM cortex A8512 DDR3 RAM4 GB on board Storage

3. Introduction to Beagle Boards :Beagle boards are tiny computers with all the capabilities of today’s desktop machine.To teach open source hardware and software capabilitiesProduced by Texas Instruments in association with Digi-Key and Newark element14Developed as a demonstration of OMAP (Open Multimedia Application platform) System on Chip (Soc)CPU: ARM Cortex A8Supported OS: Linux, Minix, FreeBSD, Android, Symbian, RISC OS

4. Beagleboard – Rev. C

5. Hardware - BeagleboardOMAP3530 (Soc) forms the core of the board.Uses Package on Package stacking of memory on top of OMAPMemory: 256MB NAND, 256MB DDR SDRAMInterfaces:DVI-D (via HDMI connector), JTAG, RS232, USB2 OTGStereo In, Stereo Out, S-Video, USB2 HostExpansion Header: I2C, I2S, SPI, MMC/SDCan be USB bus powered or take DC power

6. Using the BeagleboardBooting:NAND -> USB-> UART -> MMC (For Beagle Board)USB -> UART -> MMC -> NAND (For processor)Uses U-Boot (Universal Boot loader)Provides a simple Command Line Interface to manipulate hardware prior to booting a kernelMMC/SD is the only way to bring up a new board.

7. Beagleboard - Software Distributions you can use:AngstromUbuntuAndroid (Google’s open source software stack for mobile devices)Number of other embedded Linux distros.

8. Developing for BeagleboardOpenembedded (OE):Provides an easy to use build environmentCollection of metadata about software packagessupport for many hardware architecturesruns on any Linux distributionCross CompilationOther options:Use the Android SDKBuild your own toolchainStart from a ready made image

9. BeagleBoneAnnounced in the end of October 2011The BeagleBone is a barebone development board with a Sitara ARM Cortex-A8 processor720 MHz, 256 MB of RAMTwo 46-pin expansion connectorsOn-chip EthernetA microSD slot and a USB host port A device port which includes low-level serial control and JTAG hardware debug connections, so no JTAG emulator is required.

10. BeagleBone Features :Built-in networkingRemote accessFile systemUse many different programming languagesMultitaskingLinux softwareOpen Source

11. BeagleBone Black

12. Component Locations

13. Connector and switch Locations

14. 4 LEDs

15. Lets start with basic: LEDSThere are four user LED(s) on the Beaglebone. The user LED(s) are Accessible from user space on the file system at this location: /sys/class/leds/There is one directory per user LED, named as shown below: /sys/class/leds/beaglebone::usr0/ (GPIO1_21)/sys/class/leds/beaglebone::usr1/ (GPIO2_22)/sys/class/leds/beaglebone::usr2/ (GPIO2_23)/sys/class/leds/beaglebone::usr3/ (GPIO2_24)

16. On-board LED:Write the following commands in your terminal (First one is for turning ON and latter for OFF):USER0 : heartbeat indicator from the Linux kernel.USER1 : SD card accessUSER2 : activity indicator. Turns on when the kernel is not in the idle loop.USER3 : Onboard eMMC is access.

17. Comparison :

18. U-Boot :Universal Boot loader for embedded systemsLocating and loading the kernel with the set argumentsSetting up the argumentsInitializing additional hardwareMakes booting from serial and USB port possible

19. Boot Modes :eMMC Boot (MMC1)Uses onboard memoryDefault boot modeFastestSD Boot (MMC0)uSD cardSerial BootBoots from serial portsUSB Boot (USB0)Boots from USB

20. Booting Options :Without holding the boot button :eMMC BootuSD BootSerial BootUSB BootHolding the boot button :uSD BootUSB BootSerial Boot

21. BBB interfacing :InitializationExportInputDirectionLogicChanging the valuesOutputDirection

22. BBB interfacing with Stepper MotorConnector NumberBBB PINNumberPIN DescriptionPIN connects to stepper motor connected FRCFunctionP91,2 GNDGND(25pin)GNDP95 VCC(5V)VCC(26pin)VCCP911 GPIO0[30]FRC-21pinOutP912 GPIO1[28]FRC-22pinOutP913 GPIO0[31]FRC-19pinOutP914 GPIO1[18]FRC-20pinOut

23. Embedded System ProcessorsA number of choice available for embedded processorsTwo categories are:Standalone Processors Requires external chipset to form complete systemIntegrated Processors SoC: System on Chip

24. Standalone ProcessorsDedicated exclusively to the processor functionsNeeds external controllers to interfacing with surroundings. E.g. DRAM controller, keyboard controller and serial portsHighest Overall CPU performance.

25. Standalone Microprocessor Based System

26. Standalone Processors: ExampleMany standalone processors in 32 bit and 64 bit exist and widely used in embedded systems:IBM 970FX : A high performing 64 bit capable stand alone processor.Superscalar architecture: Core can fetch, decode and execute for more than one instruction at a time (Deeply Pipelined)Used also in IBM blade server platform

27. Standalone Processors: ExampleIntel Pentium MOne of the most popular x86 architecture for 32 and 64 bit.Super scalar architecture like IBM 970 FX.Used in many earlier laptops and commercial embedded systemsIntel AtomWidely used in notebooks and embedded system applications. Known for low power consumption

28. Integrated Processor :SoC

29. SoCA microchip that has all the components to run the system.Integrates all the components of computer in a single chipMajority of embedded application uses Integrated processors (SoC)BeagleboardProcessor TI OMAP3530 SoC - 720 MHz ARM Cortex-A8 core

30. ARM TIMELINE :1985: Acorn Computer Group manufactures the first commercial RISC microprocessor. (ARM – I . . . V)1990: Acorn, Apple and VLSI based Technology group = Advanced RISC Machines (A.R.M.). 1991: ARM6, First embeddable RISC microprocessor. 1993 : ARM7, the first multimedia microprocessor is introduced.Users :SamsungAtmelPhilipsEtc.

31. ARM :

32. Advanced RISC Machine :Instructions are same size : 32 bitInstructions are executed in 1 cycleLoad/Store access memoryAdvantage:Number of transistors are less compared to similar CISC architecture.Less hardware results in less die sizeLow power consumption

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34. Advanced Features Thumb: A new 16 bit instruction set called thumb is made available.This is less powerful instruction set but quite useful for application that do not require full power of 32 bit instructions.Advantage: High Code Density (Higher amount of code in per unit memory area)MMU and MPU: Desktop system requires it.It depends on application requirement in embedded systemARM processor can be implemented with MMU and MPU or with one of them or neither of them.

35. Advanced FeaturesDebug Interface:There is chip testing unit called JTAG (joint testing action group) interface.JTAG standard defines a set of interface for testing hardware and initial code. Jazalle DBX: (Direct Byte code Execution)Some ARM processors have direct execution support for byte code in hardware.Useful in devices for execution games and java application that otherwise require a heavy JVM.

36. Advanced FeaturesVector Floating Point UnitHardware support for floating point computationCache:The first ARM processor with Cache is ARM3. It had 1 KB chip of 4 KB.ARM 7 had a cache of 8 KB.

37. Advanced FeaturesFast MultiplierEven though ARM is a RISC processor, there are many features that do not conform to RISC philosophyARM processors may have a fast multiplier hardware unit.Synthesizable: Design Code (RTL) is available with License, using which extensions and modification are possible in basic core

38. Advanced FeaturesEmbedded ICE (In Circuit Emulator) Macrocell:The current hardware trend is to design system as macrocells.The ARM core could be considered as macrocell and other units may also be added as (e.g. peripheral units) macrocells.Some processor has embedded ICE macrocell for testing.Used for debugging and have registers to set watch points and breakpoints .

39. Naming Conventions for ARMExample: ARM7TDMI

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43. ARM CORTEXLatest in ARM is cortex seriesBased on architecture V7 version: THUMB-2 technology (Both 16 and 32 bit supported)No need to switch between ARM and THUMB instruction setCortex has well defined profile for different application areas:ARM

44. Cortex ProfilesA profile: For High End applications in Embedded Systems with modern OS. (e.g. Android)ARMv7-A architectureUsed in Mobile phones and Video SystemsR Profile:For high end application on systems with Real time capabilitiesARMv7-R architectureUsed in safety critical systemsM profile:Designed for Core embedded microcontroller type systemsARMv7-M architectureUsed in control applications

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46. Advanced Features :Data bus width :32 bit data bus32 bit read/write in 1 cycleComputational capability:RISC Approach provides good computationsRISC architecture with few CISC add-onsLow Power:Power savingOperates at low clock frequencies60MHz to 1 GHz

47. Advanced Features :Multiple Register Instructions :Data processing with registers mostlyProcessing instructions do not use addressing modes that uses one operand in memory.But, instructions for loading and storing data to registers.DSP Enhancement:Additional DSP features

48. Pipelining :Dividing instruction processing in sub-stages3 Stage pipeline: (ARM-7)Fetch – Decode – Execute5 Stage Pipeline: (ARM-9)Fetch – Decode – Execute – Buffer - Write(ARM-10) – 6 stage pipelineDrawback:Problem with branch instructionsDue to sequence change some instructions are discardedLoss of data, computation timeHigher penalty with more stages

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50. Instruction Set ArchitectureProgrammers view of computer architectureConsists of :Instruction SetsAddressing ModesRegisters etc.Basic ISA of all ARM processor are more or less same

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56. CPSR (Current Program Status Register)Bit Nos.NotionInterpretation0 to 4ModeSpecifies the current mode of operation5TState : ARM = 1 or THUMB = 06FDisables (F=1) FIQ7IDisables (I=1) IRQ8 to 23Undefined25 to 26Undefined24JJ=1 means in Jazalle state27QSticky Overflow flag28 to 31V C Z NCondition flags

57. CPSRN: Negative (N=1 indicates negative results)Z: Zero ( Z=1 indicates result is 0) C: Carry V: Overflow

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59. Exception Priorities :Reset (Highest)Data abortFIQIRQPrefetch abortSWI, undefined instruction (Lowest)

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61. Data Type6 data types in all:Signed and unsigned32 bit/ 16 bit and 8 bit operations supportedProcessing tool offers the option of storing data in little endian and big endian formatsData Alignment:For word (32-bit) should have least 2 bits of address as 0Eg: 0x1200For unaligned data like 0X1201(32 – bit ) will access 2 memory cycles 1 @ 0x12001, 2 @ 0x1204

62. Assembly Language Rules :LabelOpcode / Instruction fieldOperand fieldCommentLabel ADD R1,R2,R3 ;Add instruction

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64. Shift and RotateTwo types of shifts are possibleLogical and ArithmeticLSL (Logical Shift Left): For a 32 bit register, shift left (a specified number of times) results in shifting every bit left and vacant bits at right are filled with zeroesThe last bit shifted out from the left is copied to the carry flagLeft shift by one bit position corresponds to multiplication by 2.An LSL of 5 implies multiplication by 32

65. Shift and RotateLSR (Logical Shift Right)Similar to LSL but shifts bits in rightVacant bits at left filled by zeroes.The last bit shifted out is retained in carry flagShifting right by 1 bit is equivalent to dividing the number by 2.Two right shift cause a division by 4

66. Shift and RotateASR (Arithmetic Shift Right):Vacant bit in the left is filled with MSB of the original number.This type of shift has the function of doing ‘sign extension’ of dataThere is not instruction for Arithmetic Shift Left

67. Shift and RotateROR (Rotate Right)Data is shifted rightThe bit shifted out from right is inserted back through left.The last bit rotated out is available in carry flag.There is no Rotate Left instruction, because left rotate ‘n’ times can be achieved by rotating right ‘32-n’ times.For example rotating 4 times to the left is achieved by rotating 32-4 = 28 times to the right

68. Shift and RotateRRX (Rotate Right Extended):This corresponds to rotating right though the carry bit.Bits dropped off from the right side is moved to CF and the carry bit enters through the left of the data.

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70. Format of Shift and Rotate InstructionThe number of bit position by which shift or rotate operation need to be done is specified by a constant or another register.Example:LSL R2,#4 ; shift left logically the content of R2 by 4 bit positionASR R5,#8 ; Shift right arithmetically the content of R5 by 8 bit positionROR R1, R2 ;Rotate the content of R1 by the number specified by R2

71. ProblemThe content of some of the registers are given as:R1=0xEF00DE12R2=0x0456123FR5=4R6=28Find the result in destination register for following:LSL R1, #8ASR R1, R5ROR R2, R6LSR R2, #5

72. SolutionR1=0xEF00DE12R2=0x0456123FR5=4R6=28Find the result in destination register for following:LSL R1, #8 (Ans: 0x00DE1200)ASR R1, R5 (Ans: 0xFEF00DE1)ROR R2, R6 (Ans: 0x456123F0)LSR R2, #5 (Ans: 0x0022B091)

73. Combining the operation of Move and ShiftMOV R1, R2, LSL #2MOV R1, R2, LSR R3In both ,instruction R1 is the destination register.In first instruction, the source operand i.e. content of R2 is logically shifted left twice and then moved to R1.In second instruction, amount of shifting is specified by R3.

74. ProblemR5= 0x72340200 and R2=4FindMOV R3, R5, LSL #3MOV R6, R5, ASR R2

75. ProblemR5= 0x72340200 and R2=4FindMOV R3, R5, LSL #3 (R3=0x91A01000)MOV R6, R5, ASR R2 (R6=0x07234020)

76. Conditional ExecutionAn important and distinguished feature of ARMInstruction is executed only if specified condition is true.In general, all data processing instruction are expected to affect conditional flags.But in ARM, we must suffix the instruction with ‘S’ for this to happen. ‘S’ suffix in data processing instruction causes the flags in CPSR to be updated.

77. ExampleMOV R3, R5, LSL #3No affect on carry flat and N flag in CPSRMOVS R3,R5, LSL #3The MOV instruction is made conditional by suffixing it with S.C and N flags are now set.This flag setting can be used to make an instruction following it to be conditional.

78. Recap: Carry FlagThe carry (C) flag is set when an operation results in a carry, or when a subtraction results in no borrow.In ARM, C is set in one of the following ways:For an addition, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise.For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.For non-additions/subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.For other non-additions/subtractions, C is normally left unchanged.

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80. Detailed Format :

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84. Question :What will be the result :ADD R1, R2, R2, LSL #3RSB R3, R3, R3, LSL #3RSB R3, R2, R2, LSL #4SUB R0, R0, R0, LSL #2RSB R2, R1, #0

85. Solution :What will be the result :ADD R1, R2, R2, LSL #3 R1 = R2 + 8 R2RSB R3, R3, R3, LSL #3 R3 = 8R3 – R3RSB R3, R2, R2, LSL #4 R3 = 16R2 – R2SUB R0, R0, R0, LSL #2 R0 = R0 – 4R0RSB R2, R1, #0 R2 = 0 – R1

86. Q. Write a small assembly program for ARM, required that 2 numbers stored in R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal Put it in R9.

87. Q. Write a small assembly program for ARM, required that 2 numbers stored in R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal Put it in R9.SUBS R3, R1, R2 ;R3 = R1 – R2MOVEQ R9, R1 ;IF R1=R2 / Z=1 . . . R1 -> R9 MOVHI R10, R1 ;IF R1 > R2 / C=1 . . . R1 -> R10;MOV R10, R2;MOVLS R10,R2 ;if R1<=R2 , C=0|Z=1 , move R2 to R10

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89. Flag setting after compare InstructionIfCZR3>R410R3<R400R3=R411

90. TST InstructionTST is similar to compare, but it does ANDing and then sets conditional flags.If the result of ANDing is zero, then zero flag is set.It can be used to verify at least one of the bits of a data word is set or not.Write instruction to verify the LSB of a word in register R1 is set or not.TST R1, #01

91. TEQ InstructionTEQ does exclusive ORing which tests for equality.If both operands are equal then only zero flag is set.TEQ R1,#45

92. Data Processing Instructions :

93. Multiplication :

94. Example :MUL R1,R2,R3MULS R1,R2,R3MULSEQ R1,R2,R3MULEQ R1,R2,R3UMULL R1, R2, R3, R4

95. Branch Instructions :B BranchBL Branch and LinkBX Branch and ExchangeBLX Branch and Exchange with LinkEg :<Label> B NewSTOP B STOP<Label> BNE New<Label> BHI New

96. Assembly Programming in ARMTwo kind of statements :Executable statementsDirectives (related to assembler)AREAENTRYRNENDDefining data

97. Directives :ENTRYEntry point of first executable instructionENDAREAAREA <NAME_OF_REGEION> , CODE/DATA, READONLY/READWRITEEg. AREA SORT,CODE,READONLY

98. Directives :Defining DataNUMS DCB 9, 10, 15NUM1 DCW 0x6787, 0x4565NUM2 DCD 0x00000123, 0x67890900RNGiving variable names to registersX RN 1Y RN 10EQUEquateFACT EQU 35ASD EQU 0x40004000

99. Question :Write a program to find 3X + 4Y + 9Z , WHERE X = 2Y = 3Z = 4

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101. Program to calculate factorial of 5 numbersWrite down an ARM assembly program to calculate factorial of 5.Instructions Involved:MUL SUBSBNE

102. Solution AREA FACTO, CODE ;Define the code area ENTRY ;entry point MOV R1, #5 ;R1=5 MOV R2,#1 ;R2=1REPT MUL R2, R2, R1 ;R2=R2XR1 SUBS R1, R1, #1 ;R1=R1-1 BNE REPT ;Branch to REPT if Z!=0B B STOP ;last line END ;End

103. Subroutine/ProceduresAnother kind of branch used in Subroutine calls – BL (Branch and Link)When a BL encountered (control transfer to new sequence of instruction OR the new procedure) ARM saves current PC value in Link register.PC then starts with new instruction set (Branch Target).At the end of procedure , LR is copied to PC

104. Finding 3X2 + 5Y2 , where X=8 and Y=5 AREA PROCED, CODE ENTRY MOV R2, #8 BL SQUARE ADD R1,R3,R3 , LSL #1 MOV R2, #5 BL SQUARE ADD R0,R3,R3,LSL #2 ADD R4, R1, R0STOP B STOPSQAURE MUL R3, R2, R2 MOV PC,LR END

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107. ExampleThe constant value being added to Rn is immed_8 rotated right by 2*rotate_imm.

108. Constants :Only decimal values within range 0 – 16320 can be created using this schema.Instructions MOV, MVN can also be used with ROR

109. Literal PoolsLiteral Pool is a lookup table used to hold literals during assembly and execution. Literals : Written exactly as it is meant to be interpreted. Example: x=125 ; x is variable, 125 is literalTake an example of immediate operand MOV R1, #0x33333333Assembler will give error that such constants cannot be generated.To avoid the situation we can write:LDR R1, = 0x33333333(This is a pseudo instruction for assembler)

110. Literal PoolsLDR R1, =0x33333333The pseudo instruction forces the assembler to check for one of the following possibilitiesCan the constant be constructed with MOV or MVN combined with rotation? Assembler places the value in literal pool and generated and LDR with program relative addressMemory Space after ENDLTORG statement

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112. ExampleLDR R3,[R2, LSL #2]The effective address is the content of R2 left shifted by 2 (multiplied by 4)STR R9, [R1,R2, ROR #2]The effective address is specified by R1 and R2 and a right rotationLDR R4,[R3,R2]The effective address here is sum of R3 and R2STR R5,[R4, R3, ASL #4]The effective address is the sum of content of R4 and the arithmetically left shifted (by 4) content of R3

113. Bytes, Half Words and WordsARM has instruction to transfer specifically a word (32 bits), half word (16 bits) or a byte 8 bits) between memory and registers.Load InstructionDescriptionStore InstructionDescriptionLDRLoad WordSTRStore WordLDRHLoad Half WordSTRHStore Half WordLDRSHLoad Signed Half WordLDRBLoad ByteSTRBStore ByteLDRLoad Signed Byte

114. ProblemMemory areas are referenced by two registers R1=0x00001200, R2=0x40001100LDR R3,[R1]LDRB R3,[R1]LDRH R3, [R1]STRB R3,[R2], provided that R3= 0x 00002356AddressByte Stored0X 00001200560X 00001201230X 000012020D0X 00001203AE

115. Solution:LDR R3,[R1]R3 = 0xAE0D2356LDRB R3,[R1]R3 = 0x00000056LDRH R3, [R1]R3 = 0x00002356STR R3,[R2], provided that R3= 0x AE0D2356AddressByte Stored0X 40001100560X 40001101230X 400011020D0X 40001103AESTRHSTRB

116. Loading Signed Numbers :R7 = 0xCDEF8204LDR R1, [R7] R1 = 0xCDEF8204LDRSH R1, [R7] R1 = 0xFFFF8204LDRSB R1, [R7] R1 = 0x00000004

117. Indexed Addressing ModesPre Indexed Addressing ModesLDR R0, [R7,#4]R7 is the base register and effective address is R7+4 . The data at effective address is copied to R0.Add ! For write back optionLDR R0, [R7,#4]! R7 = R7 + 4;Post Indexed Addressing ModeLDR R0, [R4],#4The data pointed by R4 is first copied to R0. Then the content of R4 is changed to R4+4

118. Multiple Load and Store (LDM and STM)Multiple register load means that multiple memory locations are to be accessed and loaded into multiple registers.There is a base register acting as pointer to the first memory location to be accessed.The register then incremented or decremented to point the next memory locationLDM/STM{condition} address-mode Rn {!} , reg-list

119. LDM and STMSuffixes used with LDM and STMIA : Increment AfterIB : Increment BeforeDA : Decrement AfterDF : Decrement BeforeLDMDA R0,{R4-R9}32 bit word pointed by R0 is copied to R432 bit word pointed by R0-4 is copied to R532 bit word pointed by R0-8 is copied to R6and so on ........ till R9.

120. LDMIA R10,{R9, R1-R3} 32 bit word pointed by R10 is copied to R1 32 bit word pointed by R10+4 is copied to R2 32 bit word pointed by R10+8 is copied to R3 32 bit word pointed by R10+12 is copied to R9

121. The STM instructionSame format as LDMSTMIA R1, {R2-R4}Equivalent to the following instructionSRT R2, [R1]STR R3, [R1,#4]STR R4, [R1,#8]

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124. ARM9: Major Improvements over ARM7Decreased heat production and lower overheating risk.Shifting from a three-stage pipeline to a five-stage one lets the clock speed be approximately doubled, on the same silicon fabrication process.Cycle count improvements. Many unmodified ARM7 binaries were measured as taking about 30% fewer cycles to execute on ARM9 cores.Some ARM9 cores incorporate "Enhanced DSP" instructions, such as a multiply-accumulate, to support more efficient implementations of digital signal processing algorithms.

125. ARM 9Implement Harvard Architecture: The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data.

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128. ARM9: LPC 29XX ARM MCUThe LPC29xx consists of:An ARM968E-S processor with real-time emulation supportAn AMBA multi-layer Advanced High-performance Bus (AHB) for interfacing to the on-chip memory controllersTwo DTL buses for interfacing to the interrupt controllerThree or four ARM Peripheral Buses (APB) for connection to on-chip peripherals

129. ARM9 : Advanced Microprocessor Bus Architecture The ARM’s AMBA protocols are an open standard, on-chip interconnect specification.It specifies the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

130. ARM9 : AHB and APBAHB stands for Advanced High-performance Bus APB sands for Advanced (sometimes ARM) Peripheral Bus. Both are part of the Advanced Microprocessor Bus Architecture (AMBA).Dedicated AHB to APB bridges are used to interconnect.

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132. ARM Cortex M3Cortex-M3 ProcessorThe ARM Cortex-M3 processor is the industry-leading 32-bit processor for highly deterministic real-time applications Specifically developed to enable partners to develop high-performance low-cost platforms for: Microcontrollersautomotive body systemsIndustrial control systems wireless networking and sensorsLPC17XX

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