development Riunione gruppo ATLAS Roma 2 19122017 Luca Pizzimento Salvatore Bruno Elio Alunno Camelia Development of the frontend in Si Ge technology The new FE in development October ID: 791478
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Slide1
RPC
Front-end & Read-out
development
Riunione gruppo ATLAS Roma 2
19/12/2017
Luca Pizzimento, Salvatore Bruno, Elio Alunno Camelia
Slide2Development of the front-end in Si-
Ge
technology
The new FE in
development
October Testbeam FE system
& FE final
design Work in progress
Simulation
and test of a TDC with 100
ps
resolution
Atlas TDC
descriptionFunctions of the blocksResultsFuture StepOptimization of RPCs read-out panel with electromagnetic simulation Different type of read-out panel simulationOptimizationState of the art
Summary
Slide3LHC Phase 2 RPC Front-End
LHC Phase 1 RPC Front-End
Discriminator
Amplifier
TDC
RPC Strip
Serial
Output
The new Front-End in development
Luca Pizzimento
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Discriminator
Amplifier
Pull Up System
&
LVDS Transmitter
RPC Strip
LVDS Output
Slide4Figure 3
: Operating principle of custom charge
amplifier
in Silicon technology
The new Amplifier
developed for the RPCs is made in
Silicon Bipolar Junction Transistor
technology. It is based on the concept of a fast charge integration with the possibility to match the input impedance to a transmission line. The working principle of this amplifier is shown in Figure 3. The performance of the silicon BJT amplifier are shown in the following
table
.
Table 2
: Performance of custom charge amplifier in Silicon BJT technology
1000
The new Front-End in development
Luca Pizzimento
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Slide5The new full-custom Discriminator
circuit dedicated to the RPCs for high rate environment is developed by using
the Silicon-Germanium HJT technology.
The
main idea behind this new discriminator is the limit amplifier. If the signal surpasses the threshold, it will be amplified until saturation giving as output a square wave.
Input
Output
Pull up
System
Without signal
Time
V+
Voltage
V-
V+
V-
With signal
The principle of
SiGe
heterojunction
bipolar transistor
(
HJT
)
is to introduce a Silicon-Germanium impurity in the base of the transistor. The advantage of this device is that the band structure introduces a drift field for electrons into the base of the transistor, thus producing a ballistic effect that reduces the base transit time of the carriers injected in the collector. The net effect is to improve the transition
frequency and to introduce a directionality in the charge transport allowing a much lower value of B-C capacitance;
hence a much higher charge amplification can be achieved.
The new Front-End in development
Luca Pizzimento
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Slide6Figure 6
: Minimum pulse width of the new Si-Ge prototype with the simulated
and the ideal behavior of a discriminator compared
Figure 5
: Dynamic of the time-over-threshold of the discriminator prototype in
SiGe
HJT
technology.
The main features are:
Optimal characteristic function with the possibility of an easy regulation of the threshold from a minimum value of few
m
V (see Fig. 4)
Very small transition region of around 300
μ
V, practically negligible when the discriminator is used within the RPC (see Fig 4).
Time-over-threshold measurement directly with the discriminator (see Fig 5). Minimum pulse width of 3 ns ; for shorter signal the discriminator goes into a charge regime with a threshold in charge (see Fig 6).Figure 4: Characteristic function of the discriminator in Si-Ge HJT technologyThe new Front-End in developmentLuca Pizzimento4
Slide7Discriminator
Amplifier
Pull Up System
&
LVDS Transmitter
RPC Strip
LVDS Output
FE-
board
October
testbeam
Front-end system
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Slide8Discriminator
Discriminator
Transmitter
Amplifiers
Strips
Amplifier Properties
- Si standard component
- Amplification factor: 2-4 mV/
fC
- Power Consumption: 3-5 V 1–2 mA
- Bandwidth: 100
Mhz
8-channels Front-End Board composed by the new amplifier, the new discriminator ASIC and the full-custom LVDS transmitter
Discriminator Properties
-
SiGe
full custom
- Power Consumption: 2-3 V 4-5 mA
- Threshold: 0.5 mV
Bandwidth: 100 MHz
Out LVDS
The new Front-End final design
Luca Pizzimento
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Slide9Work in progress
Completing the analysis of the BIS7-8 FE prototype at H8
Final prototype FE board production & test
Completing the Discriminator ASICs & FE boards full order for the BIS 7-8 production
Luca Pizzimento
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Slide10Development of the front-end in Si-
Ge
technology
The new FE in
development
October
Testbeam
FE system
& FE final
design
Work in
progress
Simulation
and test of a TDC with 100
ps resolutionAtlas TDC descriptionFunctions of the TDC blocksResultsFuture stepOptimization of RPCs read-out panel with electromagnetic simulation Different type of read-out panel simulationOptimizationState of the art
Summary
Slide11ATLAS
TDC
The ATLAS TDC will be organizer in 8 scaler at 9 bit, connected at the same VCO. Each scaler needs to have 9bit output to cover the
iter
Buntch
crossing period.
T
he
IN_CH # signals are managed by out discrimination coming from the RPCs strips
. The
serializer
block is designed to store and serialize the output 9 bits of the counters by sending them to an FPGA that will collect all the data of a single
RPC.
T
echnology used : BiCMOS –SiGe 130nm IHP electronic IN_CH8Serial.1Serial.2
Serial.3
Serial.7
Serial.8
Data
acquisition
CK
USA15
Write-
Shift
Latch1
N
0
N
1
N
7
N
8
Latch2
N
0
N
1
N
7
N
8
Latch3
N
0
N
1
N
7
N
8
Latch7
N
0
N
1
N
7
N
8
Latch8
N
0
N
1
N
7
N
8
IN_CH7
IN_CH3
IN_CH2
IN_CH1
9bit
Slide12VCO operation
Varying
the supply voltage of a logic gate, we can control the transit time of a signal that passes through
it.
We repeated the measurements at different times and different temperatures.
Range Frequency oscillation Vs
voltage
applied
Power consumption of the
VCO
In
this
test,
we
supplied
voltage
only
to the VCO.
The oscillations at the higher voltages are caused
because we applied a higher voltage respect the foundry specifications.
Slide13Each
s
caler is realized by a counter and a block of memory.
A
counter is called synchronous when the counting input
is
applied simultaneously at every flip-flop so they commute at the same time. This configuration allows it does not depend on commutation time of the flip-flop
.
From the
simulations made, this device can count up to when the input signal at a frequency not higher than 1.5GHz.
CK
iN
2GHz
CK in 1.5GHz
Simulation of a progressive binary count.
The state of the counter is read by a memory block. This block has the
purpose to read and
send
the state of the
counter
at
the
serializer
.
SCALER 9bit (
synchronous
counter
)
(
Schematic
of
scaler
at
9bit.)
Slide14PISO
–
parallell
in Serial Out (
serializer)
The 9 bit of the counter are memorized and send at the FPGA by this register.
The synchronism
between TDC and FPGA is managed by the
ck
emptying
.
In this device is present ad control pin (
write-0&shift-1)
that the ability to upload data of the counter and send this data to the FPGA. The serialized data can be sending to the FPGA up to 2GHz, in this moment is not possible download the data at this speed because not exist FPGA that acquiring so fast.(Schematic of a serializer at 9bit.)
write
(0)
Shift
(1)
Data IN
REset
Ck
emptying
(2GhZ)
Serial
OUt
Slide15Layout work
in progress
159um
69um
Slide16Result
–
intrinsic
Jitter
The time difference,
measured on a sample of 954
events, shown a
Gaussian distribution with a
rms
of
15,2ps
. This
rms
mast
be divider for since it corresponds to the difference of two value, giving 10,77ps that is the intrinsic jitter of the TDC. An initial test consisted in measuring the intrinsic jitter of the VCO, which represents the ultimate limit of the TDC precision. This was done by measuring time interval in-between the rising edges of two consecutive pulses produced at 100 MHz rate with a precision of 5 ps.
(
Schematic
of first prototipe)
Result
–
second
prototipe
=
2.8GHz =>
=350ps
This was done by measuring time interval
between
the rising edges of two consecutive pulses produced at
40
MHz rate with a precision of
5 ps
.
Scaler
Latch
E
IN_CH
The time difference,
measured on a sample of
10k events, shown a
Gaussian distribution with a
rms
of
100ps.
This
rms
mast
be
divider for
since
it corresponds to the
difference
of two
value.
Future step
Design a prototype of TDC for
the BI RPCs
- 8
TDC channels with serialized
output;
Test and study the outputs
to check the integrity and proper operation of the device.
Studying
, designing and
optimization of
the coupling between Discriminator and TDC.
The
communication protocol between the TDC and the data acquisition
system, compatible
with the FPGA. The pre-production will be carried out through small-volume production of the Europractice foundry service.
Slide19Development of the front-end in Si-
Ge
technology
The new FE in
development
October
Testbeam
FE system
& FE final
design
Work in
progress
Simulation
and test of a TDC with 100
ps resolutionAtlas TDC descriptionFunctions of the blocksResultsFuture StepOptimization of RPCs read-out panel with electromagnetic simulation Different type of read-out panel simulationOptimizationState of the art
Summary
Slide20CST Studio Suite
Excitation
method
:
Waveguide
port
Plane
wave
Discrete
port
Solver:
-
Transient solverFrequency solverBased on FIT algorithm (Finite Integral Equations) which performs the resolution of the integral Maxwell equations applied on a discretized version of the model Mesh
Slide21R
ead - out panel
simulation
Floating
GroundWire
Adapted
NoGround
Slide22Simulation
Input
signal
distribution
@
different
𝜎
𝜎 = 7mm (1/4
pitch
)
𝜎 = 13mm (1/2
pitch
)
𝜎 = 26mm (1 pitch)𝜎 = 52mm (2 pitch)𝜎 = 78mm (3 pitch)
Slide23Simulation
results
Slide24Simulation
results
Slide25Optimization
of the model
GroundWire
-
Parametric
sweep
of 𝛿 : ground
strip width
(𝛿= 0.5 mm Standard)
𝛿 = 0.1 mm
𝛿 = 1.5 mm
Slide26Optimization
of the model
GroundWire
Slide27Optimization
of the model
GroundWire
Slide28𝛿 = 0.1 mm
𝛿 = 1 mm
𝛿 = 1.5 mm
Optimization
of the model
GroundWire
Slide29𝛿
= 1
mm
𝛿 = 1.5 mm
Optimization
of the model
GroundWire
Slide30Out
signals
, 𝛿 = 1.5 mm
Cluter
Size
= 8Efficienza vs 𝛿
Crosstalk compared to 𝛿 = 0.5 mm (standard):
0.1 mm: +5.7%1 mm: -8.6%1.5 mm: +330%
Cs
1mm/
CS
xmm
Optimization
of the model GroundWire
Slide31State of the art
Slide32State of the art
Slide33State of the art
Slide34State of the art
Slide35State of the art
Slide36Back up
Slide37Slide38An
open collector
is a common type of output found on many integrated circuits (IC), which behaves like a switch that is either connected to ground or
disconnected. Instead
of outputting a signal of a specific voltage or current, the output signal is applied to the base of an internal NPN transistor whose collector is externalized (open) on a pin of the IC. The emitter of the transistor is connected internally to the ground pin
.
Open Collector
Advantages of Open Collector circuit:
Interface different families of devices that have different operating voltage levels.
Withstand a higher voltage than the chip supply voltage.
Wired logic connection; more than one open-collector output can be connected to a single line.
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