PPT-Managing DRAM Latency Divergence in Irregular GPGPU Applications

Niladrish Chatterjee Mike OConnor Gabriel H Loh Nuwan Jayasena Rajeev Balasubramonian Irregular GPGPU Applications Conventional GPGPU workloads access vector or matrixbased data structures. Niladrish. . Chatterjee. Manjunath. . Shevgoor. Rajeev . Balasubramonian. Al Davis. Zhen Fang. ‡†. Ramesh . Illikkal. *. Ravi . Iyer. *. University of Utah , NVidia. ‡. and Intel Labs*. †. K. . Qureshi. ECE, Georgia Tech. Gabriel H. Loh, AMD. Fundamental Latency Trade-offs. in Architecting DRAM Caches. MICRO 2012. 3-D Memory Stacking. 3-D Stacked memory can provide large caches at high . Performance Characterization of. Irregular . GPU Kernels. Molly A. O’Neil and Martin Burtscher. Department of Computer Science. Introduction. GPUs as general-purpose accelerators. Ubiquitous. in high performance computing. Bank Privatization for Predictability and Temporal Isolation. Sungjun. . Kim . Columbia . University. Edward A. Lee . UC . Berkeley . Isaac . Liu . UC Berkeley. Hiren. D. Patel University of Waterloo. Jared . Coplin. and Martin . Burtscher. Department of Computer Science. 1. Introduction. GPU-based accelerators. Used in high-performance computing. Spreading in PCs and handheld . devices. 2. Power Characteristics of Irregular GPGPU Programs . Graphics Processing Unit (GPU). GPU is the . chip . in computer video cards, PS3, Xbox, . etc. Designed to realize the 3D graphics pipeline. Application .  Geometry  Rasterizer image. GPU development:. DRAM Scaling. Prof. Onur Mutlu. http://www.ece.cmu.edu/~omutlu. onur@cmu.edu. HiPEAC. ACACES Summer School 2013. July 15-19, . 2013. The Main Memory System. Main memory is a critical component of all computing systems. K. . Qureshi. ECE, Georgia Tech. Gabriel H. Loh, AMD. Fundamental Latency Trade-offs. in Architecting DRAM Caches. MICRO 2012. 3-D Memory Stacking. 3-D Stacked memory can provide large caches at high . Reducing Branch Divergence in GPU Programs. . T. D. Han and T. Abdelrahman. GPGPU 2011. Reading. T. D. Han and T. Abdelrahman, “Reducing Branch Divergence in GPGPU Programs,” GPGPU 2011. Goal. Improve the utilization of the SIMD core. Access Locality. Hasan Hassan,. Gennady . Pekhimenko. , . Nandita Vijaykumar, . Vivek. . Seshadri. , Donghyuk Lee, Oguz Ergin, . Onur. . Mutlu. Executive Summary. Goal. : . Reduce average DRAM access latency with no modification to the existing DRAM chips. by Exploiting the Variation in Local . Bitlines. . Jeremie S. Kim. . Minesh. Patel . Hasan Hassan . Onur. . Mutlu. . Motivation. : DRAM latency is a . major performance bottleneck. Problem. Computer Architecture Lecture 6b: SoftMC Hasan Ibrahim Hasan ETH Zürich Fall 2018 4 October 2018 SoftMC A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies Charge-Level-Aware Look-Ahead Partial Restoration. Yaohua. Wang. 1,2. . Arash. Tavakkol. 1. Lois Orosa. 1,4. . Saugata. . Ghose. 3. . Nika Mansouri Ghiasi. 1. . Minesh. Patel. Unclonable. Functions . by Exploiting the Latency-Reliability Tradeoff . in Modern Commodity DRAM Devices. Jeremie. S. Kim. . Minesh. Patel . Hasan Hassan . . Onur. . Mutlu. . Motivation.