PDF-WP395 (v1.1) May 19, 2015www.xilinx.com

. Part 1. Objectives. After completing this module, you will be able to:. Describe the dedicated block memory resources in the 7 series FPGAs. Describe the different block memory modes available. Describe the capabilities of the built in FIFO. Part 1. Objectives. After completing this module, you will be able to:. Describe the primary usage models of DSP slices. Describe the DSP slice in the 7 series FPGAs. DSP Overview. 7 Series FPGA DSP Slice. Objectives. After completing this module you will be able to…. Apply global timing constraints to a simple synchronous design. Use the Xilinx Constraints Editor to specify global timing constraints. Part 1. Objectives. After completing this module, you will be able to:. Describe the control sets of the slice flip-flops . Identify the implications of the control sets on packing. Control Sets. Designing. Xilinx Training. Welcome. If you are new to FPGA design, this module will help you estimate your FPGA power consumption. These design techniques promote fast and efficient FPGA design development. Performance (MHz). The . Xilinx Embedded Developer Kit. Xilinx Training. Welcome. If you are new to Embedded design with Xilinx FPGAs, this module will help you start planning your design. Understanding the difference between Xilinx’s FPGA architectures is essential if you are going to select an appropriate FPGA device family. DataPath. Engine Group Project. Matt Slowik. Porting DPE to Xilinx FPGA environment, Component Integration. test_dpe_top.v. dpe_top.v. DP. RQS. QS. CTL. t. op.v. driver. User application. top_debug.v. Xilinx . Analog Mixed . Signal Solution. HDL Design . Flow. . Note: Agile Mixed Signal is Now Analog Mixed Signal. Welcome. If you are a FPGA designer, this module introduces the HDL flow for Xilinx Agile Mixed Signal solutions . Part 1. Fundamentals of . FPGA Design. 1. day. Designing for. Performance. 2. days. Advanced FPGA. Implementation. 2. days. Intro to VHDL or . Intro to Verilog. 3. days. FPGA and ASIC Technology Comparison. Part 1. Objectives. After completing this module, you will be able to:. Identify and differentiate the members of the 7 series families. 7 Series FPGA Families. Logic Cells. 20K – 355K. 70K – 480K. Slice and I/O Resources. Objectives. After completing this module, you will be able to:. Describe the CLB and slice resources available in Spartan-6 FPGAs. Describe flip-flop functionality. Anticipate building proper HDL code for Spartan-6 FPGAs. Slice and I/O Resources. Objectives. After completing this module, you will be able to:. Describe the CLB and slice resources available in Virtex-6 FPGAs. Describe flip-flop functionality. Anticipate building proper HDL code for Virtex-6 FPGAs. Part 1. Objectives. After completing this module, you will be able to:. Describe the clocking resources available in the 7 series FPGAs. Explain the contents of the Clock Management Tile (CMT). Add these resources to your design. Part 1. Objectives. After completing this module, you will be able to:. Describe the new I/O features for supporting high speed memory controllers. Overview. Phaser. and I/O FIFOs. Memory Controller .