S.Vereschagin , Yu.Zanevsky - PowerPoint Presentation

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S.Vereschagin, Yu.Zanevsky, F.LevchanovskiyS.Chernenko, G.Cheremukhina, S.Zaporozhets,A.Averyanov

R&D FOR TPC MPD/NICA READOUT ELECTRONICS

Varna, 2013

Laboratory of High Energy Physics, JINR,

Dubna

, Russia

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CONTENS1Introduction (general characteristics of TPC/MPD, & readout electronics requirements)FEE prototype (FEC-64) Main option FEE (FEC-128 & RCU)Conclusions

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General view of the MPD detector2

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TPC/MPD3

12 Readout

chambers

HV-electrode

~28 KV

Field cage

beam

beam

~110000

readout

channels

E

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Main parameters of the TPC4Size: 3.4m(length) x 2.8m (diameter);

Drift gas: 90% Ar+10% Methane CH4 or 90%Ar+10% CO2;Drift velocity: 5.5 cm/us(Ar

+ CH4), 2.3 cm/us (Ar + CO2); Length of drift volume: 1.7 m;

Data readout:

2x12 sectors (MWPC, cathode pad readout

);

Maximal

event rate 5

kHz;

Total

number of

pads

~ 110000

;

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Simulation results5

Central collision on TPC/MPD @ 9GeV

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Main parameters of the FEE TPC6Total number of channels ~ 110000

Data stream from whole TPC – 5 GB/sLow power consumption – less then 100 mW/ch

Fast optical transfer interfaceBased on ASIC and FPGA

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Front-End Electronics prototype7

FEC-64 channels

PASA chip 16 channels ASIC(

low noise amplification

of the signal

)

ALTRO chip

16

channels ASIC

(

digitization and signal processing)

FPGA - board control

Signal to noise ratio,

S/N - 30



NOISE

<

1000

e- (С=10-20

pF)

Dynamic Range - 1000 Zero suppression Buffer (4 / 8 events) FTDI USB2.0 (prototype only)

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Processing in PASA & ALTRO8

-

FWHM – 190ns

- Baseline restoration after 1

m

s:

~ 5 % in amplifier / shaper

~ 0.1% in dig. chip

PASA

ALTRO

- Baseline corrections

- Tail cancellation

FWHM ~ 190ns

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FEE TESTING9

FEE on the TPC prototype

Pulse after amplification

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FEC-64 testing software 10

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Block diagram of FEE base11

RCU

Switch 1

FEC 1

FEC 8

FEC 1

FEC 8

Switch 8

Pad Plane ~4500

ch.

128

ch.

DAQ PC

Slow

control

Group 1

Group 8

Trigger

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FEE of RoC general diagram12

RCU

FEC

group

FEC

group

FEC

group

FEC

group

FEC

group

DAQ PC

Ethernet

Slow

Control

system

Switch

Trigger System

Switch

Switch

Switch

Switch

5 Gb/s

HLT TPC

Optical interface

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TPC/MPD READOUT OUTLINE13Support high data throughput & maximum parallelization;HLT

(TPC), online reconstruction & events compression;Use GPU NVIDIA for computing trigger decision;Like ALICE, ATLAS & CBM experiments;

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DATA READOUT14

PC 1

PC 24

HLT

HLT TPC

Event builder

From other detectors

Permanent Data Storage

Online reconstruction

HLT

decision to MPD central trigger processor

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Maximum parallelization15

ROC 1TPC

FEE

HLT - TPC

GPU BOARD

PCI-E 8 Gb/s and more

MB-PC

ROC 24

TPC

FEE

FEE

PCI-E 1x

PCI-E 1x

PCI-E 1x

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Conclusions:16Prototype card has been designed 6 prototype cards has been produced & tasted

Testing software was developed (LabView & C++)Base FEE concept was developed

FEE design toward final version ongoing

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I would like to express our gratitude for the help to17 Victor

Chepurnov (JINR)

Stepan

Razin

(

JINR)

Alexander

Moskovsky

(JINR)

Luciano

Musa (CERN)

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Thank you for your attention!

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Final version of FEE

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Basic version of FEC

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Switch node

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Readout Control Unit

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Choice of FPGA technologySRAM, where the programmable switch is controlled by an SRAM memory cell.Flash (or EPROM/EEPROM), where the switch is a floating gate transistor that can be turned off by injecting charge onto the floating gate.Antifuse, where an electrically programmable switch forms a low resistance path between two metal layers.