Konstantin Androsov INFN Pisa amp University of Siena Massimo Minuti INFN Pisa Fabrizio Palla INFN Pisa Stamatios Poulios INFN Pisa amp University of Siena ID: 1001872
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1. First look at data compressionKonstantin Androsov – INFN Pisa & University of SienaMassimo Minuti – INFN PisaFabrizio Palla – INFN PisaStamatios Poulios - INFN Pisa & University of Siena
2. Introduction (1/2)Target: CMS pixel detectorHit rate estimation for inner barrel layer at 140 Pile-Up is about 2 GHz/cm2Expected high readout rate (~ 4.8 Gbits/s per chip for 1MHz trigger rate)2.4 Gbits/s max bandwidth per chip (2 E-links)2First look at data compression
3. Introduction (2/2)An efficient transfer protocol should be developed to collect all measurements and ensure good detector performanceLossless compression with decreased output rate to reduce the usage of linksFor 1 MHz L1 trigger accept rate and 320 MHz working clock:320 clock cycles available!!!First look at data compression3BeforeAfterRaw dataLinksCompressed DataLinks
4. SimulationBPIX Layer1: 3.0 cm, abs(z) < 26 cmCell geometry: 25(bending)x100(beam)x150(thickness) μm31 module = 1x4 chipsNumber of columns per module (chip) : 648 (162)Number of rows per module (chip) : 648 (648)Digitizer threshold: 1500 electronsTotal number of simulated events: 50Used 5bit ADC for 560 electrons per ADC count.First look at data compression4SIM results provided by E. Migliore.
5. Pixel distributions5Number of active pixels per chipNumber of clusters per chipNumber of pixels per clusterFirst look at data compression
6. Readout formatUsing readout format proposed in the draft of Phase 2 pixel system and read-out chipDefault hit data representation:(30 bits/pixel)Pixel 124 bit Address5 bit ADC1 bit flagEvent header32-bitEvent trailer32-bitHit data…Event size, check sum, status/error flag,…BX-id, event ID, chip address, statusPixel 2Pixel N…6First look at data compression
7. Default representationExpected(Optimal encoding)Alphabet entropy X and Y entropy is high that makes costly to send unprocessed coordinates per each pixel Results(No compression)big tails…7First look at data compression
8. Characteristic distribution8Pixel XPixel YActive ADCFirst look at data compression
9. Arithmetic compression2 approachesSingle pixel representation (without zero suppression)Delta representation (zero suppressed data)Arithmetic encoding is a form of entropy encoding used in lossless data compression00.360.540.600.60.91abc0.540.5760.5940.60.5760.58680.59220.594acbExample:P(a)=0.6P(b)=0.3P(c)=0.1Phrase: “acb”9First look at data compression
10. Arithmetic Compressor – HDL implementationclkenstartletterread_letterend_bitstart_bitbitvalidmem_addmem_datainmem_selmem_wenreg_addreg_datareg_wenEncoding LogicSymbol Prob. MemoryConfiguration & StatusRegisters-) 32-bit Arithmetic Encoding Logic;-) 2 X 32 X 4 bytes symbol Mem.;-) Configuration & Status regs;dataout10First look at data compressionFIFO_empty
11. Synthesis/Simulation resultsArithmetic Compressor logic synthesis (IBM 130nm SC library):cells 49918 Area 95843 μm2Power 75,05 mW@320MHzArithmetic Compressor Logic HDL simulationperformed on L1 simulated data.Current performance:3 clock cycles per pixel (all pixels)10.4 clock cycles per pixel (active pixels only) = 4.43 → 2.34 clk/(output bit) Further optimizations expected.1 clk/(output bit) 11First look at data compression
12. Single pixel representationxyCompression ratio 1.5 tails are reducedBits per chip per eventAverage is close to the expected with an optimal encoding12First look at data compression
13. Delta representationSending (Dx=xn-xn-1, Dy=yn-yn-1, adc) for each pixelPosition entropy depends on pixel ordering:Pixel orderingH DxH DyH pixel positionBy columns5.461.677.13By arrival6.703.019.71By rows2.253.705.95Encoding column by columnEncoding in horizontal direction by pixel arrivalEncoding row by row13Bits per chip per event(ordering by rows)First look at data compression
14. Delta Representation(ordering by rows)xyFIFO col 0FIFO col 1FIFO col 2FIFO col 3(x1, adc1)(x2, adc2)(x3, adc3)(x2, adc4)FIFO row x1FIFO row x2FIFO row x3(x1, y0, adc1)(x2, y0, adc2)(x2, y2, adc4)(x3, y2, adc3)Dx encoderDy encoderADC encoderPackage data14First look at data compression
15. Conclusions and next stepsBest solution: Delta representation.Arithmetic encoding with delta representation: doable for splitting the chip in four regions and encode in parallelMax number of active pixel per chip 400100 pixels per region3 sequences x 4 regions = 12 compressorsArea estimation for 65nm: 12x0.095(mm2)/4 = 0.285 mm2 Dynamic power consumption estimation for 65nm:P65 = 12*(65/130)*(1/1.4)2*P130 = 230 mW1st task: Fully debug and optimize current arithmetic compressor.Next steps:Improve power consumptionSynthesize/simulate on 65 nmVerify the functionality of the algorithm for delta representation 15First look at data compression
16. Thank you !First look at data compression16This project has received funding from the European Union’s Seventh Framework Programme for research, technological development and demonstration under grant agreement no 317446