ABSTRACT TIs DP83640 precision PHYTER implements timecritical portions of the IEEE 1588 Precision Time Protocol PTP allowing high precision IEEE 1588 node implementations These same features ID: 12385
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ApplicationReport SNLA104AApril2008RevisedApril2013 AN-1838IEEE1588BoundaryClockandTransparent ClockImplementationUsingtheDP83640 ..................................................................................................................................................... ABSTRACT TIsDP83640precisionPHYTERimplementstime-criticalportionsoftheIEEE1588PrecisionTime Protocol(PTP),allowinghighprecisionIEEE1588nodeimplementations.Thesesamefeaturescanbe usedtoimplementmulti-portboundaryclock(BC)andtransparentclock(TC)devicesaswell. Contents 1Introduction..................................................................................................................2 2BasicRequirements........................................................................................................2 2.1PHYAddressing....................................................................................................3 2.2SynchronousEthernet.............................................................................................3 3IEEE1588ClockControl..................................................................................................3 3.1VerificationofTimeSetting.......................................................................................3 4IEEE1588BoundaryClock................................................................................................4 4.1RecommendedTimestampDelivery............................................................................5 5End-to-EndTransparentClock............................................................................................5 5.1SyncMessageHandling..........................................................................................5 5.2DELAY_REQMessageHandling................................................................................6 5.3ClockSynchronizationandSyntonization......................................................................6 6Peer-to-PeerTransparentClocks.........................................................................................6 6.1SyncMessageHandling..........................................................................................6 6.2PeerDelayMechanism...........................................................................................6 6.3PeerDelayResponse.............................................................................................7 6.4ClockSynchronizationandSyntonization......................................................................7 7PerformanceResults.......................................................................................................7 8Conclusions..................................................................................................................7 9References...................................................................................................................7 ListofFigures 1ReferenceClockandManagementInterfaceConnections...........................................................2 2GPIOConnectionforTimeVerification..................................................................................4 3SynchronizationVersusNumberofBoundaryorTransparentClocks...............................................7 PHYTERisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 1 SNLA104AApril2008RevisedApril2013 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated Introductionwww.ti.com 1Introduction BoundaryclocksandtransparentclocksarebothmechanismstoprovideaccuratedistributionofthePTP protocolacrossmulti-portnetworkcomponentssuchasbridges,routers,andrepeaters.Applications rangefromlargemulti-portEthernetswitchestotwoorthreeportdaisychaindevices.Aboundaryclock maybeslavedtoamasterononeportandactasmasteronallotherports.Atransparentclockdoesnot actasamasterorslave,butinsteadsforwardsPTPeventmessagesandprovidescorrectionsforthe residencetimeacrossthebridge.Inallcases,eachtransparentorboundaryclockincludesasinglePTP clocktoaccuratelysynchronizedevicesacrossthenetwork. TheDP83640yieldsahighlyaccuratesolutionwhilereducingtheamountofadditionalcircuitryrequiredto implementtheclockandtimestampfeaturesofanIEEE1588capableboundaryclockortransparentclock device.Sincetimestampingisdoneinternaltothephysicallayerdevice(PHY),thetimestampsareequally deterministicinallmodesofoperation,providingforthehighestaccuracysolution. 2BasicRequirements Inaboundaryclockortransparentclock,thereshouldonlybeonePTPclockthatissharedbyallports. SinceeachDP83640precisionPHYTERincludesanindependentinternalPTPclock,twobasic requirementsmustbemet.ThefirstisthatallofthePHYdevicesmusthaveasharedreferenceclock source.ThisiseasilymetbyhavingasinglereferenceclocksourcewhichprovideseachPHYwiththe samereferenceclock,usuallythroughsomeformofclockdistribution. ThesecondrequirementisthateachofthePTPclocksmustbeabletobecontrolledsimultaneously.This isnecessarytoensurethatallPTPclocksmaybesettothesametimeandsettorunatthesame adjustedrate.Thismaybeaccomplishedusingabroadcastwriteoperationsupportedbytheserial managementinterface.Foradescriptionofthebroadcastwriteoperation,seetheDP83640Datasheet. Theserialmanagementinterfacesupportsoperationupto25MHzonMDC.Thereferenceclock connectedtoX1oneachPHYshouldbe25MHzforMIIoperationor50MHzforRMIIoperation.Itisalso possibletousea25MHzreferenceforRMIIbyusingRMIImastermode(seeAN-1794UsingRMII MasterMode(SNLA101)). Inadditiontothebasichardwareconnectionsforthedevice,theBCorTCmustincorporateacontrollerto handleoperationoftheprotocolaswellasgeneration,termination,andmodificationofPTPpackets.The natureofthepackethandlingisdependentonthetypeofdevicebeingimplemented.Theseisdiscussed inseparatesections. Figure1.ReferenceClockandManagementInterfaceConnections 2 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation SNLA104AApril2008RevisedApril2013 UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated www.ti.comIEEE1588ClockControl SincetheMDCsignalisalsousedasaclock,aclockdistributionnetworkmayalsoberequiredonMDC toensureacleanclocksignalateachPHY. Figure1showsanexampleofapossibleconnectionforthereferenceclockandmanagementinterface signals. 2.1PHYAddressing SincethebroadcastwritefunctionusesPHYaddress0x1F,theboundaryortransparentclockdevice shouldnothaveanyPHYstrappedtoaddress0x1F. Inaddition,PHYaddress0forcesaPHYtopower-upinanisolatestate.Ifadeviceisstrappedtophy address0,managementaccessesarerequiredtoexittheisolatestate. AllotherPHYaddressesareavailableforusewithoutrestrictions. Sinceonly31PHYdevicesmayresideonaserialmanagementinterface(oneaddressisreservedfor broadcast),ifmoredevicesarerequired,additionalserialmanagementinterfacesmustbeprovided. 2.2SynchronousEthernet InadditiontonormalEthernetoperation,theDP83640maybeusedina100MbsynchronousEthernet mode.Inthismodeofoperation,allportsmayusetherecoveredclockononeportasthereferenceclock forallotherports.InaPTPsystem,thisallowsthefrequencyofthegrandmasterclocktopropagate throughtheentirenetwork.FormoredetailsofthesynchronousEthernetoperation,seeAN-1730 DP83640SynchronousEthernetMode:AchievingSub-NanosecondAccuracyinPTPApplications (SNLA100). 3IEEE1588ClockControl ThebasicPTPclockcontrolsareindependentofthemodeofoperation,thatis,boundaryclockversus transparentclock.Inanodedevice,aslavewillupdatethePTPclockbasedontheinformation determinedfromthePTPmessagetimestamps.Thisamountstosettingtheratebasedonameasured ratedifferencerelativetothemaster.Italsoincludessettingthetimeandcorrectingfortimeoffsetfrom themasterasmeasuredbytheprotocol.Inaboundaryclockortransparentclock,thePTPclockcontrol willoccurinasimilarmanner,withonesignificantdifference.ClockcontrolchangesaremadetoallPTP clocksratherthanjustasingleclock.Asmentionedpreviously,thiscanbedoneusingthebroadcast mechanismsupportedovertheserialmanagementinterface.Therefore,allclockchangeswillbemadeto eachPHYPTPclocksimultaneously. 3.1VerificationofTimeSetting Toensurethetimecorrectionsaremadeaccurately,itmaybedesirabletoverifythePTPclocktime valuesusingtheGPIOcapabilitiesintheDP83640.Thiscanbedonebyconnectingasignalbetweena GPIOpinoneachPHY.Forexample,aconnectioncanbemadebetweenGPIO9oneachPHYasshown inFigure2. 3 SNLA104AApril2008RevisedApril2013 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated IEEE1588BoundaryClockwww.ti.com Figure2.GPIOConnectionforTimeVerification Theclocktimescanbeverifiedandcorrectedusingthefollowingalgorithm: 1.EnableeventtimestampcaptureonGPIO9foreachPHY. 2.EnabletriggeroutputonaGPIO9forPHY1. 3.Generateasingletriggerpulse,whichshouldbecapturedoneachPHYincludingPHY1. 4.ReadeventtimestampsfromeachPHY. 5.MakecorrectionstoallPHYsbasedondifferencewithcapturedtimestampfromPHY1. Thisprocedureshouldonlyberequiredattheinitialtimesetting.Allsubsequentsettingsshoulduseastep adjustmentortemporaryrateadjustment,whichshouldoccurateachPHYwithoutintroducinganyerror. ThemainreasontoverifytheinitialtimesettingisduetothesynchronizationofsignalsintothePHY. SincetheMDCclockmaybeasynchronoustothereferenceclockusedinthePHY,theremaybeasmall errorintheinitialPTPclocktimesduetosamplingoftheMDCsignalbythePHY. 4IEEE1588BoundaryClock Aboundaryclockcanbeusedtosupportbothversions1and2oftheIEEE1588specification.The boundaryclockimplementsalocalPTPclockwhichcanbesynchronizedtoamasterononeportandact asamasteronotherports.SinceaboundaryclockisafullPTPclockimplementation,boththetimeand frequencymustbesimultaneouslyupdatedtothelocalPTPclocksoneachPHY.TheprocessingofPTP messagesanddeterminationoftimeandratechangesmustbedoneonalocalprocessor.Thebasic processingoperationsrequiredoftheboundaryclockare: IdentifyandrouteallinboundPTPmessagestothelocalprocessor.TerminateallPTPtraffic. ImplementationofthebestMasterclockalgorithmorothermechanismfordeterminingmasterand slaveportassignments. Synchronizeasaslaveontheportconnectedtothebestmaster. Masteroperationforallotherports. SimultaneouscontrolallPHYPTPclocks,includingtheclockintheSlaveport. 4 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation SNLA104AApril2008RevisedApril2013 UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated www.ti.comEnd-to-EndTransparentClock 4.1RecommendedTimestampDelivery Timestampscanbedeliveredtothecontrollerusingseveralmethods.Thebasicmethodistoread timestampsusingtheserialmanagementinterface,utilizingtheMDCandMDIOpairofsignals.However, tominimizeinformationtransferovertheserialmanagementinterface,itisrecommendedthatthe boundaryclockusetheinbandmechanismsoftimestamptransferwhenpossible. EnabletimestampinsertionforreceivePTPeventmessages.Thiseliminatestheneedtoreadthe receivetimestampoverMDIO.Italsoeliminatesissueswithmatchingtimestampstopacketssincethe timestamparrivesembeddedinthepacket. Useone-stepoperationforsendingSyncmessages.Thiseliminatestheneedtoreadthetransmit timestampoverMDIOandalsoeliminatestheneedtosendaFollow_Upmessage. UseDelay_ReqtimestampinsertionforsendingDelay_Reqmessages.Thiseliminatestheneedtoread thetransmittimestampoverMDIOasthetimestampwillarriveembeddedintheDelay_Respmessage. Ifaportontheboundaryclocksupportsthepeerdelaymechanism,thetransmittimestampsfor PDelay_ReqandPDelay_RespmessageswillprobablyneedtobereadusingMDIO. TimestampscouldalsobedeliveredusingPHYStatusFramesiftheamountofreceivedatatrafficisnot expectedtobetoosignificant.FormoreinformationonPHYStatusFrames,seetheDP83640Software DevelopmentGuide. 5End-to-EndTransparentClock Version2oftheIEEE1588specificationintroducestransparentclocksasanalternativetoimplementing boundaryclocksformultiportdevicessuchasbridges,switchesorrouters.Thefirsttype,theend-to-end transparentclock,forwardsPTPeventmessages,butmodifiesthemessagesfortheresidencetimefor themessagetopropagatefromaningressporttoanegressport.Correctionsmustbemadeforthe propagationofbothsyncandDelay_Reqmessages. 5.1SyncMessageHandling Therearetwooptionsforhandlingsyncmessages:two-steporone-stepoperation. 5.1.1SyncTwo-StepOperation Fortwo-stepoperation,boththeingressandegresstimestampsneedtoberecordedandsavedto calculatetheresidencetime.Thesyncmessageshouldbeforwardedwithoutmodification.Iftimestamp insertionisusedtodeliverthereceivedsynctimestamp,thereservedtimestampinsertionfieldsshouldbe clearedbeforeforwardingthepacket.UponreceiptofanassociatedFollow_Upmessage,theresidence timeshouldbeaddedtothecorrectionFieldoftheFollow_Upmessage.NotethatifaPTPmessage arriveswithoutthetwo-stepflagset,thetransparentclockneedstosetthetwo-stepflaginthesync message,andgenerateaFollow_UpmessagetodelivertheresidencetimeinthecorrectionField. 5.1.2SyncOne-StepOperation Theone-stepoperationoftheDP83640maybeutilizedtoeliminatethetimestamptransfersacrossthe managementinterface.WhilethespecificationcallsforaddingtheresidencetimetothecorrectionField, thesameresultsmaybeobtainedbyaddingtheincomingoriginTimestamptothecorrectionFieldand subtractingtheingresstimestamp.Upontransmission,theegresstimestampforthesyncmessagewill automaticallybeinsertedintotheoriginTimestampfield.Theprocessorshouldset: correctionField=correctionField+originTimestamp-sync_ingress_timestamp originTimestamp=0 Usingone-stepoperation,thePHYwillautomaticallyset: originTimestamp=sync_egress_timestamp SincethecorrectionFieldonlysupportsa16-bitsecondsfield,thisonlyworksifthelocalPTPclockforthe TCissynchronizedwithin215secondsofthemasterclock.Beforeforwardingthefirstsyncmessage,the transparentclockshouldfirstsetthePTPclocktimeandthenmodifytheingresstime-stampbasedonthe adjustedtime. 5 SNLA104AApril2008RevisedApril2013 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated Peer-to-PeerTransparentClockswww.ti.com 5.2DELAY_REQMessageHandling ForDelay_Reqmessages,theDP83640doesnotsupportamechanismtoaddtheresidencetimetothe correctionFieldoftheDelay_Reqmessage.Instead,boththeingressandegresstimestampsmustbe recordedfortheDelay_Reqmessage.Thesetimestampsareusedtodeterminetheresidencetimethat willbeaddedtothecorrectionFieldoftheassociatedDelay_Respmessagereturnedfromthemaster.As theremaybeoutstandingDelay_Reqmessagesfrommultipledownstreamslaves,theprocessormay needtostoremultipleresidencetimevalues.NotethattheDelay_Reqtimestampinsertionisnot applicablefortransparentclockoperationasthefeatureisonlyforusewhenthereisasingle,localsource forsendingDelay_Reqmessages. 5.3ClockSynchronizationandSyntonization Formostaccurateresidencetimemeasurements,thePTPclocksineachPHYshouldbysyntonizedwith thegrandmaster.Syntonizationonlyrequirescorrectiontothefrequencyandis,therefore,simplerthan fullsynchronization.Theprocessorcanusetheingresstimestampsfromsyncmessagestodeterminea ratecorrectionrequiredforthePTPclock.AllPHYclocksshouldbemodifiedasdescribedpreviously usingthebroadcastwriteovertheserialmanagementinterface.Whilethelocalclocksarenotrequiredto besettothesametimeasthegrandmaster,theyshouldbeinitiallysettothesametimeaseachother. Alternatively,syntonizationmaybehandledontheprocessorwithoutadjustingtherateofthePHYclocks. TheratecorrectionmaybeusedtomodifythecomputedresidencetimesinsertedintoFollow_Upand Delay_Respmessages.Thismethodmaynotbeusedwithone-stepoperation.Ifsyntonizationisrequired tomultiplePTPdomains,thenthismustbehandledontheprocessor. Ifone-stepoperationisusedforsyncmessages,thenthelocalPTPclocksmustalsoberoughly synchronizedtothegrandmaster.Themoreaccuratethesynchronization,theclosertheoriginTimestamp willbetotheoriginalorigin-Timestamp.Forthislevelofsynchronization,correctionstothelocalPTPclock onlyneedtobemadeperiodicallyandonlyifthePTPclocktimevariesoutsideanacceptablerange.For timecorrections,asimplifiedoffsetfromthemastermaybecomputeddirectlyfromtheoriginTimestamp, correctionField,andsync_ingress_timestamp. 6Peer-to-PeerTransparentClocks Version2oftheIEEE1588specificationalsodefinespeer-to-peertransparentclocks,whichmeasuresthe locallinkdelaysusingthepeerdelaymechanism,ratherthanusingthedelayrequestmechanismto measurefullpathdelay.Peer-to-peertransparentclocksmustdeterminetheresidencetimeandmake correctionstosyncmessages.Inaddition,correctionsmustbeincludedforinboundpathdelaysas measuredusingthepeerdelaymechanism.SincetheDelay_Reqmechanismisnotsupportedonpeer-to- peerTCs,nospecialprocessingisrequiredforDelay_Reqmessages. 6.1SyncMessageHandling Processingofsyncmessagesisessentiallythesameasinend-to-endTCs.Themajordifferenceisthat inboundpathdelaymustbeaddedtothecorrectionFieldofthesyncorassociatedFollow_Upmessage. Eitherofthetwo-steporone-stepoperationsmaybeusedasdescribedfortheend-to-endTC. 6.2PeerDelayMechanism Asrequiredbythespecification,apeer-to-peerTCshouldperiodicallysendoutPDelay_Reqmessages oneachporttomeasurethepathdelaytothepeerattachedtothatport.OutboundPDelay_Req timestampsshouldberecordedbythePHYandreturnedthroughMDIOreads.InboundPDelay_Resp timestampsmaybedeliveredviatimestampinsertion(recommended)orviaMDIOreads.Basedonthe informationinthePDelay_Resp,andpossiblyPDelay_Resp_Follow_Up,theprocessorshouldcompute theinboundpathdelayontheport.ThisvalueshouldbeaddedtothecorrectionFieldforsyncmessages arrivingontheport. 6 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation SNLA104AApril2008RevisedApril2013 UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated www.ti.comPerformanceResults 6.3PeerDelayResponse Inadditiontoinitiatingthepeerdelaymechanism,thepeer-to-peerTCmustbeabletorespondtopeer delayrequestsoneachport.Todothis,eachPHYmusttimestampinboundPDelay_Reqmessagesand deliverthetimestamptotheprocessorviatimestampinsertionorviaMDIOreads.Theprocessorshould thensendaPDelay_RespmessageandplacetheingresstimestampforthePDelay_Reqmessageinto therequestReceiptTimestampfieldofthePDelay_Respmessage.Theegresstimestampforthe PDelay_RespmessagemustbecapturedbythePHYandreturnedtotheprocessorthroughMDIOreads. ThePDelay_RespegresstimestampshouldthenbesentintheresponseOriginTimestampfieldofa PDelay_Resp_Follow_Upmessage. 6.4ClockSynchronizationandSyntonization Clocksynchronizationandsyntonizationrequirementsarethesameasforend-to-endtransparentclocks. SeeSection5.3. 7PerformanceResults NationalhastestedsimpleboundaryclockandtransparentclockimplementationsusinganFPGA-based evaluationsystemtogenerateandforwardPTPmessages.Figure3showssynchronizationresultsfor basictestingacrossanumberofBCorTCdevices.Asabaseline,back-to-backperformanceisincluded thatdoesnotincludeaBCorTC.Testconditionsinclude: 1.1secondsyncinterval 2.25MHzcrystalorstandardoscillator 3.Eachtestlength�1000seconds Theresults(showninFigure3)wereobtainedusingadigitaloscilloscopetomeasuretheMastertoSlave offsetusingapulse-per-second(PPS)fromeachdevice. Figure3.SynchronizationVersusNumberofBoundaryorTransparentClocks 8Conclusions TheDP83640precisionPHYTERcanbeusedtoimplementIEEE1588boundaryclockandtransparent clockdevices,providingahighlyaccuratesolutionandreducingtheamountofadditionalcircuitryrequired. Timestampsarecapturedatthemostaccuratepointbyimplementingthetimestampcapabilitiesinthe physicallayer.Inaddition,theDP83640includesmechanismstocontroltheindependentPTPclocks simultaneously,providingasimplemethodtoensurethePTPclocksarealwayssynchronized. 9References IEEEP1588TMD2.2DraftStandardforaPrecisionClockSynchronizationProtocolforNetworked MeasurementandcontrolSystems(2007)InstituteofElectricalandElectronicsEngineers,Inc. DP83640SoftwareDevelopmentGuide DP83640PrecisionPHYTER-IEEE1588PrecisionTimeProtocolTransceiver(SNOSAY8) 7 SNLA104AApril2008RevisedApril2013 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated Referenceswww.ti.com AN-1730DP83640SynchronousEthernetMode:AchievingSub-NanosecondAccuracyinPTP Applications(SNLA100) AN-1794UsingRMIIMasterMode(SNLA101) NationalSemiconductorEthernetPHYTER-SoftwareDevelopmentGuide.(2007)National SemiconductorCorporation. 8 AN-1838IEEE1588BoundaryClockandTransparentClockImplementation SNLA104AApril2008RevisedApril2013 UsingtheDP83640 SubmitDocumentationFeedback Copyright©20082013,TexasInstrumentsIncorporated IMPORTANTNOTICE TexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,enhancements,improvementsandother changestoitssemiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latest issue.Buyersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentand complete.Allsemiconductorproducts(alsoreferredtohereinascomponents)aresoldsubjecttoTIstermsandconditionsofsale suppliedatthetimeoforderacknowledgment. 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