Computer Architecture Lecture 4

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Computer Architecture Lecture 4




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Presentations text content in Computer Architecture Lecture 4

Slide1

Computer ArchitectureLecture 4Sequential Circuits

Ralph GrishmanSeptember 2015

NYU

Slide2

Time and Frequencytime = 1 / frequency

frequency = 1 / timeunits of timemillisecond = 10-3 second

microsecond = 10-6 second

nanosecond = 10-9 secondpicosecond = 10-12

second

units of frequency

kiloHertz (kHz) = 103 cycles / secondmegaHertz (MHz) = 106 cycles / secondgigaHertz (GHz) = 109 cycles / second

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Slide3

Today’s ProblemA typical clock frequency for current PCs is 2

GHz. For the original IBM PC’s, it was 4.77 MHz. About how many times faster is the clock on a current PC?(a)

2.385(b

) 42 (c) 400

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d

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Slide4

Solution

New Frequency = 2 GHz = 2 * 109 Hz

Old Frequency = 4.77 MHz ≈ 5 MHz = 5 * 106 Hz

Ratio = 2 * 109 / 5 * 106

= 400

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Slide5

Combinational vs. sequential circuitsin a combinational circuit, output (after some delay) is a function of

inputsin contrast, a sequential circuit holds state information:

the output is a function of the state of the device, as well as its

inputs in other words, sequential circuits have memory

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Slide6

A very simple 2-state circuit

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Slide7

A very simple 2-state circuit1 state

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0

1

Slide8

A very simple 2-state circuit0 state

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1

0

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What’s the problem?

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Slide10

We cannot change the state

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RS LatchSolution: change from inverters to NOR gates:

when R = S = 0, has two stable states (Q = 0 or Q = 1)

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Q

R

S

Slide12

RS Latch

set: changing S to 1 forces Q=1;  when S is returned to 0, Q=1 state is retainedreset: changing R to 1 forces Q=0;  when R is returned to 0, Q=0 state is retained

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Q

R

S

Slide13

D latch

when C [clock] input is 0, latch retains current

statesetting C to 1 forces Q=D ["load data"];  when C is returned to 0, state is retained

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Slide14

D latch timing

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Slide15

RegisterA register is a set of latches with a common clock

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Slide16

Synchronous Circuita

set of registers controlled by a common clock + a

combinatorial circuit to compute the next state

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nextstate

register

C

Slide17

Synchronous Circuit: Up Counter

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+1

register

C

Slide18

Problem: counter doesn’t workReason: race condition

Solution: edge-triggered flip-flop for registerloads data only on falling edge of clock

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Slide19

Master-slave flip-flop

Loads data only on falling edge of clock

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Slide20

D flip-flop timingedge-triggered MS FF

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Slide21

How fast?How fast can we clock a synchronous circuit?

Clock period > delay of combinatorial circuit + setup and delay times of register

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Slide22

Register FileHolds all (programmable) processor registers

At a minimum, must providedata input (for register write)data output (for register read)register numberwrite signal

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Register FileA typical instruction will read two registers, do some calculation, and store the result in a third register

We can do this faster if in the same clock cycle we canread both operand registerswrite the result registerwe do this through multiple register

ports

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Register File

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Read Port

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Write Port

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A Decoder

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