EPESEFE Kamil Nicpon kamilnicponcernch EPESEFE 143003 20Nov17 1 ELMB Agenda ELMB Motivation for upgrade Investigated possibilities Solutions chosen for development 20Nov17 ID: 782289
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Slide1
ELMB++:
RADWG Meeting 20-11-2017EP-ESE-FE
Kamil Nicponkamil.nicpon@cern.chEP-ESE-FE14-3/003
20-Nov-17
1
ELMB++
Slide2AgendaELMB
Motivation for upgradeInvestigated possibilitiesSolutions chosen for development20-Nov-172ELMB++
Slide3Embedded Local
Monitor BoardTopology:CAN-bus daisy chainuC
: ATmega128Interfaces:64 analog inputs32 Digital I/OsUSART, SPIISP20-Nov-17
3
ELMB++
Slide4E
mbedded Local Monitor Board
Very compact size 50x67 mmVery low power consumptionTwo connectors with 100 pinsUsed in all experiments~20000 produced
Very cheap, 85CHF per board
Radiation tolerance:10
12 neutrons/cm2 and ~14 krad
Magnetic field up to 1.5 T
20-Nov-17
4
ELMB++
Slide5Motivation for upgrade
Obsolescence of some components (ELMB designed in the 90’) Higher level of radiation expected ~100 krad, 4 1013 1MeV neutron/cm2 SEE free ( 4 104 hadron > 20 MeV/s ) Some functionalities missing DACs, JTAG, I
2C Throughput might be higher20-Nov-175ELMB++
Slide620-Nov-17ELMB++
6Investigated solutions:
Replacement 1:1 by RadTol componentsThales Alenia DPC based
GBT-SCA based
FPGA based
Topologybus
bus
star
star
Infrastructure preserved
YES
YES
NO
NO
Functionality
no gain
extended
upgraded
upgraded
Powering scheme
flexible
local
local
flexible
Form factor preserved
YES
possible
NO
NO
Throughput
low
low
Moderate
High
Slide7Approach I: 1:1 RadTol components
Replacement of all components for their radiation tolerant versionsIdea recently reconsidered: Might be used in lower radiation areas
ProsConsInfrastructure preserved
Fast design process
Backwards compatibility
No real upgrade
No proven
radiation tolerant replacement for all parts.
20-Nov-17
7
ELMB++
Slide8Approach II: Thales Alenia DPC
No drift up to at least 60kRadSEU hardened > 40 MeV.cm2/mgHas most of desired functionalities
However:
No embedded memory
Not power efficient
Requires to design a package
Time
Commitment 200k€
Block diagram of DPC
20-Nov-17
8
ELMB++
Slide9Approach II: Thales Alenia DPC
No drift up to at least 60kRadSEU hardened > 40 MeV.cm2/mgHas most of desired functionalities
However:
No embedded memory
Not power efficient
Requires to design a package
Time
Commitment 200k€
Block diagram of DPC
20-Nov-17
9
ELMB++
DISCARDED
Slide10Slow Control Adaptor for GBTStar topology with GBTX via e-linkFeatures:31
analog inputs4 analog outputs 32 GPIOsJTAGSPII2CApproach III: GBT-SCA
20-Nov-1710ELMB++
Slide11GBT-SCA: Star topology with GBTx
8 Analog Outputs
62 Analog Inputs
SCA
JTAG, I2C, SPI
64 Digital I/O
SCA
GBTx
(40 E-links)
Back-end FPGA
Counting Room
2x E-link
Optical Link
Drawbacks:
Heavy back-end
Additional costs of GBTx, VTRX etc.
20-Nov-17
11
ELMB++
Approach III: GBT-SCA
Slide12GBT-SCA: Infrastructure issues
2 SCA needed to replace every ELMB (# of analog inputs)Topology: daisy chain starE-link is based on SLVS interfaceFavourable AC coupled transmission line because of long lines
Ground of the chip is a ground reference for ADCGBT-SCA: Protocol issues
Request-response scheme
(e.g. Reading one input requires few transactions)
one
ADC measurement ~
160us
Not possible to introduce DC-balanced coding
for e-link
20-Nov-17
12
ELMB++
Approach III: GBT-SCA
Slide13E-link: eye diagram for 50m Cat5 (F/UTP) cable
Eye wide open – very promising in terms of lengths.Noticeable length difference between each pair: manufacturer dependent.Problem for GBTx – SCA link
20-Nov-1713ELMB++Approach III: GBT-SCA
Slide14GBT-SCA: Star topology w/o HUB
8 Analog Outputs
62 Analog Inputs
SCA
JTAG, I2C, SPI
64 Digital I/O
SCA
Back-end FPGA
Counting Room
Optical Link
Drawbacks:
Very h
eavy back-end
High additional costs per board
Profits:
Radiation Hard, tested and proven
GBTx
20-Nov-17
14
ELMB++
Approach III: GBT-SCA
Slide15Approach IV: Star topology with Antifuse
FPGA
A
nalog Outputs
Analog Inputs
JTAG, I2C, SPI
Digital I/O
s
Satellite with AX Series FPGA
HUB
with
GBTx
or FPGA
(40 E-links)
Back-end FPGA
Counting Room
E-link
Optical Link
20-Nov-17
15
ELMB++
Approach
IV: FPGA based
Slide16Satellite ELMB++ architecture
A
nalog Outputs
Analog Inputs
JTAG, I2C, SPI
Digital I/O
s
AX Series FPGA
AC
coupling
E-link
interface
8-ch
ADCs
1-ch
DACs
DC/DC
DC/DC
Digital isolation
20-Nov-17
16
ELMB++
Approach
IV: FPGA based
Slide17Key components for FPGA-based Satellite:Antifuse
FPGA: Microsemi AX500 or AX1000 (~$120 or ~$220)ADCs: ADS7852Y 8-channel, 12-bit, parallel output (~$4 per piece)DACs: MAX5541 1-channel 16-bit, SPI interface (~$5 per piece)Digital Isolation: ADuM3402, quad-channel 3V-5.5V 5V/3.3V Transceiver SN74LVC2T45
20-Nov-1717ELMB++Approach IV: FPGA based
Slide18Current Firmware:
- 1x SPI/JTAG master- 1x I2C master- 4x
ADCs parallel read-out-32 Digital I/OsResource usage:1577 R-cells2103 C-cells
59% of R-cells (AX500)
39% of C-cells (
AX500)20-Nov-17
18
ELMB++
Approach
IV: FPGA based
Slide19Strength of the design - ADCs
4 conversions simultaneously
Controller ready to execute other commands related to SPI, I2C, Digital I/
Os while ADC conversion is running
Conversion results are stored in FIFO and queued with lower priority in relation to other tasksTime between two conversions: ~5.2us
Two modes: ONE_SHOT and BURST
20-Nov-17
19
ELMB++
Approach
IV: FPGA based
Slide20Not one, but three paths for development
Replacement 1:1 by
RadTol componentsGBT-SCA basedFPGA basedForm, function and infrastructure preservedYESNONO
Radiation level
30 krad
70 Mrad
100
krad
Flexibility
NO
NO
YES
Grounding
scheme
Flexible
Local
Flexible
Throughput
Low
Moderate
High
20-Nov-17
20
ELMB++
Summary
Slide21Thank You
20-Nov-1721ELMB++