status A Mekkaoui A 50 m X50 m Pixel current status VDDA VDDD GND D GNDA A 50 m X50 m Pixel Global pins VDDA VDDD GND D GNDA Analog Bias and global Control M6 shielded with M5 next slides ID: 658900
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Slide1
A 50mx50m pixel: floorplan statusA. MekkaouiSlide2
A 50mX50m Pixel :current status
VDDA
VDDD
GND
D
GNDA
Slide3
A 50mX50m Pixel : Global pins
VDDA
VDDD
GND
D
GNDA
Analog Bias and global Control: M6 shielded with M5 (next slides)
Power: AP//M9//M8 Slide4
A 50mX50m Pixel
: local Pins
Digital Bloc starts here
Local configuration bits: M2 x8 ; M3 x1; (M1 thru M3 is possible)
Access is at the boundary of the analog cell. No pin pickup inside the analog
Discriminator output M2 (M1 thru M3 is possible).
Needs to be immediately inverted!HitEnable and HitOrEnable config bits delegated to the logic.Slide5
A 50mX50m Pixel : Floor Plan
No switching activity allowed:
Config
bloc
Analog Frontend
No switching activity allowed:
Config blocHit InterfaceSlide6
A 50mX50m Pixel : Floor Plan
Hit InterfaceSlide7
A 50mX50m Pixel : Some Metal Restriction
Dynamic global signals => M7
M5/M4 forbidden in the green areas
Metal restrictions will be finalized when the digital powering strategy is finalized (AP -> M1
vias
problems). In progressSlide8
A 50mX50m Pixel : Symbol
Local
config
(M2)
Symbol pin position reflect layout location !
Global bias & Control (M6)1 Glorious outputSlide9
A 50mX50m Pixel : Preparing to deliver a bloc that is compatible with automatic tools. We need to formally embed the required restrictions in the design for a Digital on Top methodology.
A design guidelines/requirements document is needed. This is in progress. To enrich the discussion I have uploaded a crude document (with comments form Dario and
Tomek
) to the
indico page.Slide10
Now A different topic. Easing TOP integration and preapring for a smart redaout chip
Snapshot from FEI4
Main Memory
Huge number of lines to distribute to “remote” location
Hard to distribute and shield. Suboptimal layout Not easy to be part of an automated system
A distributed memory system using common address, data and control lines is preferred. (modular, scalable, easy to simulate with analog)Every Programmable entity (Bias DAC, PLL config, Iref, …..) would be have a predesigned common bloc or sub-bloc (4bit instead of 8 bit).Slide11
Easing TOP integration and preapring for a smart redaout chip: Standardized interface .Address buss (8)
Data Bus (8)
Control bus (3)
DAC1
DAC2
PLL
XXXX
Interface + memory
DAC proper
Control
Operation on CLK edge
000
Shift R
001
Read
010
Write
011
Set
100
Reset
101
Increment
110
Decrement
111
Shift
L
clock
Example of control table
Main target are the slow configuration, but could be used to take a snapshot of dynamic signals
Will ease automatic testing and optimization
Not all blocs need to implement all the control!Slide12
Conclusion