Pro Asic3 - Radiation test - PowerPoint Presentation

Slide1

Pro Asic3 - Radiation test at CHARM

Christophe Godichal – BE/BI/QPchristophe.godichal@cern.ch

1

Test Setup

2

Test Setup

40

GBTx

Elinks

80

lines

in the FPGA

2 use for Reset,

Enable

flag

78 use for the test

logic

3

FPGA Configuration

Test

Logic

used

52% of the FPGA

4

Test Logic

16 Shift-Register with different

combinaison of

logic

gate between register

Without logic gate between registersNOT gates

AND gatesOR gates

12 Shift-Register TMR with the same combinaison of the Shift-register without

TMR

5

Test Logic: Shift-Register

Objective: SEU detection

Register

arrangment2 SR with 350 reg. placed

« randomly » by the compiler 3 SR with 350 reg. placed manually at the extreme of the FPGA

32 bit shift

register

(

manual

placement)

32 bit shift

register

(

manual

placement)

Long connection in the fabric

6

Shift-Register with

Logic Gates

Shift-

Registers

with 8 NOT gates between

each registerObjectiveSEU detectionSET detection @40MHz2 SR with

350 reg. placed « randomly » by the

compiler3 SR with 350 reg. placed manually at the extreme of the FPGA

Shift-

Registers

with

8 AND

gates

between each registerSensibility of SEU and SET

3 SR with 350 reg. placed manually at the extreme of the FPGAShift-Registers with 8 Or gate between each registerSensibility

of SEU and SET

3 SR

with

350 reg.

placed

manually

at the

extreme

of the FPGA

7

Shift-Register With

« TMR »Shift-Registers

with

« TMR »

SEU Immune, SET in the voter3 Simple SR, 3 with 8 NOT gate

, 3 with 8 AND gate, 3 with 8 OR gate (all SR with 350 reg TMR)Test is

used to compare sensibility of Shift-

Register with TMR and without TMR

8

Results - TID

results

Type of SR

Manual Placement in

the FPGA

Placed by the Compiler

Shift-Register

TMR

Gy

Gy

Gy

SR_0

485

479

489

SR_1

499

467

478

SR_2

538

486

SR_NOT_0

513

492

475

SR_NOT_1

501

490

461

SR_NOT_2

502

494

SR_AND_0

504

481

SR_AND_1

499

477

SR_AND_2

514

474

SR_OR_0

515

511

SR_OR_1

  459SR_OR_2  485

Manual placement in the FPGA has failed from 485Gy to 538 Gy Placed by the compiler has failed from 467Gy to 492Gy Shift-Register TMR has failed from 461Gy to 511GyFPGA Stopped working at 752Gy

9

Results#

errors and Cross-Section

Type

Total

Nb

of Register

Total

Nb

of

Errors

Cross-Section

Cross Section

uncertainty

Simple

1750

267

9.14E-14

5.59E-15

Not Gate

1750

256

8.76E-14

5.47E-15

And Gate

1050

146

8.33E-14

6.89E-15

Or Gate

1050

156

8.90E-14

7.12E-15

Without

TMR

10

Results#

errors and Cross-Section

With

TMR

Type

Total

Nb

of Register

Mean (

λ)

std dev (

σ)

Cross-Section

Cross Section

uncertainty

Simple

1050

12

3.46

6.84E-15

1.98E-15

Not Gate

1050

9

3.00

5.13E-15

1.71E-15

And Gate

1050

5

2.24

2.85E-15

1.28E-15

Or Gate

1050

10

3.16

5.70E-15

1.80E-15

11

The I/O of the Shift-Register

with TMR are not TMR tooWe have 2 register in the input and 1 register

in the output port



What

is the probability to have one error

on these

i/o port ?ResultsConfidence on TMR results

Type

#I/O

reg

Cross-Section

Error I/O

reg

probability

Simple

3

9.14E-14

0.46

Not Gate

3

8.76E-14

0.44

And Gate

3

8.33E-14

0.42

Or Gate

3

8.90E-14

0.45

12

ResultsDifference

between SR not TMR and SR TMR

Type

No TMR

TMR

Improvement

σ

σ

Simple

9.14E-14

6.84E-15

13.35

Not Gate

8.76E-14

5.13E-15

17.07

And Gate

8.33E-14

2.85E-15

29.20

Or Gate

8.90E-14

5.70E-15

15.60

13

Conclusion

All shift register stopped around 500Gy

The

ProAsic

dies around 750GyWe have few errors

on TMR-ed chain, so the statistics or not really goodWe

can suppose error in the I/O cell in the Shift-

Register TMRFuture testing can be programmed

to test more in

details

the propagation

delays

14