Georgi Mitev 08112017 1 Baby MIND electronics readout scheme 08112017 2 Baby MIND Synchronization chain 08112017 3 Baby MIND WAGASCI Beam Line Spill Number 16bit ECL 34pin flat cable ID: 1043990
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1. Baby MIND – WAGASCI SynchronizationGeorgi Mitev08/11/20171
2. Baby MIND electronics readout scheme08/11/20172
3. Baby MIND Synchronization chain08/11/20173Baby MINDWAGASCIBeam LineSpill Number16bit ECL34pin flat cablePre-/Beam trigger1x NIMLemo cableECL/NIM/TTLPhillips 726NIM/TTLECLTTLECLNIMPhillips 726NIM/TTLECLTTLECLNIMDIFDIFGDCC. . .TTL -> EthernetZedBoardZynqtm-7000 DBMini-crateFEB 1FEB 2FEB 3FEB 4FEB 5FEB 6Slot 7Fan-outHDMI 1HDMI 2HDMI 3HDMI 8HDMI 9HDMI 7. . .CCC50 MHz clockFPGASpill#Trigger2161Fan-outRJ45 1RJ45 2RJ45 3RJ45 9RJ45 8. . .RJ45 10Input conditioning and isolationIsolator x16ECLLVTTLIsolator x1(x2)ECLLVDSIsolator x2LVDSLVDSXPort or LAN PhyLANLVTTLClock & SyncInternal clockCLK synthesizerPLLφSynth CtrlSerializer8b/10b EncSync LogicCommunication and settingsSP# 2SettingsSP#Start/StopTRGClk1Clk0Spill#Clock &Start/StopTriggerSpill# 2
4. MCB installation and connectivityInstalled inside the 6U VME crate alongside GDCC/CCC – available 6 slotsPowered from the crate – power requirements TBDClock signal input – LVDS on HDMI from CCCSynchronization signals – separate slideClock outputs - 8(10) CAT6 cables to the Baby-MIND FEB mini-cratesComputer control – USB or LAN connection via onboard USB/LAN serial converterRequired front panel controls/switches - TBD08/11/20174
5. Synchronization signals inputBeam/Pre-beam triggerECL levelHIF3BA-34D-2.54R connector100ns width100ms Beam-to-PreBeam pause~30us before neutrinos~2.48s periodSpill numberECL levelHIF3BA-34D-2.54R connectorTime of update – TBDSignal connectivity - TBDBackup LAN connectionRJ45 10/100MbDelay from the original - TBD08/11/20175ClockTaken from CCC50MHz frequencyHDMI connectorLVDS levelInternal clockFrequency – TBDStability - TBDStart/Stop acquisitionTaken from CCCLVDS on HDMIInternal from Beam trigger
6. Baby MIND synchronization plan B propositionBeam/Pre-beam trigger to FEB0 converter bridgeSpill numberRead SP# from ZedBoard on the DAQ PCMap FEB SP# to beam-line SP#08/11/20176
7. Backup Slides08/11/20177
8. Beam line trigger timing08/11/20178Borrowed from a slide by N. Chikuma
9. WAGASCI trigger connection08/11/20179Borrowed from a slide by N. Chikuma
10. Master Clock Board simplified diagram08/11/201710ControlClock Selector, jitter cleaner & fan-out[e.g. HMC7044]14 CML outputsMini-crate 0 ......Mini-crate 7 JapanInputSignalConditioningSYNC signalLogicClock control logicLAN LinkSettings & SP# 2 inputHW start, resetSYNC fan-outCML outputs[e.g. SY58031U x8 x2]CML outputs [e.g. CDCL1810 x10]07071111 ?Other [e.g. monitoring]M-LVDSComm. & SettingsLogicInternal ClockFPGAClockSynchronization
11. MCB input chipsNB4N527S – x2 AnyLevel-to-LVDS (10x11.6$)ADN4650 – x2 LVDS isolator (10x12.8$)Total – 244$SN10KHT5541 – x8 ECL-to-TTL (2x11.9$)ADUM140D – x4 TTL isolator (4x5.6$)NB4N527S – x2 AnyLevel-to-LVDS (2x11.6$)ADN4650 – x2 LVDS isolator (2x12.8$)Total – 95$XPort - Embedded Ethernet Device Server (~50$)08/11/201711