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ARM and Thumb Instruction Set Quick Reference Card Key to Tables Rm See Table

Shift and rotate are only av ailable as part of Operand2 A commaseparated list of register s enclosed in braces and See Table PSR fields As 574045745857445574475745257449574595746057406 must not include the PC Either CPSR Current Processor Status

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ARM and Thumb Instruction Set Quick Reference Card Key to Tables Rm See Table




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Presentation on theme: "ARM and Thumb Instruction Set Quick Reference Card Key to Tables Rm See Table"— Presentation transcript:

and Thumb-2 Instruction SetQuick Reference CardKey to TablesRm {, &#xop8.;怀sh}See Table Register, optionally shifted by constant&#xOper; nd2;.60;See Table Flexible Operand 2. Shift and rotate are only available as part&#xr8.7;eglistA comma-separated list of registers, enclosed in braces { and }.See Table PSR fieldseglist-PC&#xr8.7;.60;reglist, must not include the PC.Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register)eglist+PC&#xr8.7;.60;reglist, including the PC.Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later.+/- ARM and Thumb-2 Instruction SetQuick Reference CardOperationAssemblerS updatesActionNotesMultiplyMultiplyMUL{S} Rd, Rm, RsNZC*Rd := (Rm * Rs)[31:0](If Rm is Rd, S can be used in Thumb-2)N, Sand accumulateMLA{S} Rd, Rm, Rs, RnNZC*Rd := (Rn + (Rm * Rs))[31:0]Sand subtractT2MLS Rd, Rm, Rs, RnRd := (Rn (Rm * Rs))[31:0]unsigned longUMULL{S} RdLo, RdHi, Rm, RsNZC*V*RdHi,RdLo := unsigned(Rm * Rs)Sunsigned accumulate longUMLAL{S} RdLo, RdHi, Rm, RsNZC*V*RdHi,RdLo := unsigned(RdHi,RdLo + Rm * Rs)Sunsigned double accumulate long6UMAAL RdLo, RdHi, Rm, RsRdHi,RdLo := unsigned(RdHi + RdLo + Rm * Rs)Signed multiply longSMULL{S} RdLo, RdHi, Rm, RsNZC*V*RdHi,RdLo := signed(Rm * Rs)Sand accumulate longSMLAL{S} RdLo, RdHi, Rm, RsNZC*V*RdHi,RdLo := signed(RdHi,RdLo + Rm * Rs)S16 * 16 bit5ESMULxy Rd, Rm, RsRd := Rm[x] * Rs[y]32 * 16 bit5ESMULWy Rd, Rm, RsRd := (Rm * Rs[y])[47:16]16 * 16 bit and accumulate5ESMLAxy Rd, Rm, Rs, RnRd := Rn + Rm[x] * Rs[y]Q32 * 16 bit and accumulate5ESMLAWy Rd, Rm, Rs, RnRd := Rn + (Rm * Rs[y])[47:16]Q16 * 16 bit and accumulate long5ESMLALxy RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[x] * Rs[y]Dual signed multiply, add6SMUAD{X} Rd, Rm, RsRd := Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]Qand accumulate6SMLAD{X} Rd, Rm, Rs, RnRd := Rn + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]Qand accumulate long6SMLALD{X} RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]Dual signed multiply, subtract6SMUSD{X} Rd, Rm, RsRd := Rm[15:0] * RsX[15:0] Rm[31:16] * RsX[31:16]Qand accumulate6SMLSD{X} Rd, Rm, Rs, RnRd := Rn + Rm[15:0] * RsX[15:0] Rm[31:16] * RsX[31:16]Qand accumulate long6SMLSLD{X} RdLo, RdHi, Rm, RsRdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] Rm[31:16] * RsX[31:16]Signed top word multiply6SMMUL{R} Rd, Rm, RsRd := (Rm * Rs)[63:32]and accumulate6SMMLA{R} Rd, Rm, Rs, RnRd := Rn + (Rm * Rs)[63:32]and subtract6SMMLS{R} Rd, Rm, Rs, RnRd := Rn (Rm * Rs)[63:32]with internal 40-bit accumulateXSMIA Ac, Rm, RsAc := Ac + Rm * Rspacked halfwordXSMIAPH Ac, Rm, RsAc := Ac + Rm[15:0] * Rs[15:0] + Rm[31:16] * Rs[31:16]halfwordXSMIAxy Ac, Rm, RsAc := Ac + Rm[x] * Rs[y]DivideSigned or UnsignedRM.60;op Rd, Rn, RmRd := Rn / Rm&#xo-9.;䀀p is SDIV (signed) or (unsigned)MoveMOV{S} Rd, &#xOper; nd8;&#x.600;2NZCRd := Operand2See also Shift instructionsNMVN{S} Rd, &#xOper; nd8;&#x.600;2NZCRd := 0xFFFFFFFF EOR Operand2NtopT2MOVT Rd, #&#ximm1;怀Rd[31:16] := imm16, Rd[15:0] unaffected, imm16 range 0-65535wideT2MOV Rd, #.60;imm16Rd[15:0] := imm16, Rd[31:16] = 0, imm16 range 0-6553540-bit accumulator to registerXSMRA RdLo, RdHi, AcRdLo := Ac[31:0], RdHi := Ac[39:32]register to 40-bit accumulatorXSMAR Ac, RdLo, RdHiAc[31:0] := RdLo, Ac[39:32]:= RdHiShiftArithmetic shift rightASR{S} Rd, Rm, &#xRs|8;&#x.600;shNZCRd := ASR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, ASR &#xRs8.;怀|shLogical shift leftLSL{S} Rd, Rm, &#xRs|8;&#x.600;shNZCRd := LSL(Rm, Rs|sh)Same as MOV{S} Rd, Rm, LSL &#xRs8.;怀|shLogical shift rightLSR{S} Rd, Rm, &#xRs|8;&#x.600;shNZCRd := LSR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, LSR &#xRs8.;怀|shRotate rightROR{S} Rd, Rm, &#xRs|8;&#x.600;shNZCRd := ROR(Rm, Rs|sh)Same as MOV{S} Rd, Rm, ROR &#xRs8.;怀|shRotate right with extendRRX{S} Rd, RmNZCRd := RRX(Rm)Same as MOV{S} Rd, Rm, RRXCount leading zerosCLZ Rd, RmRd := number of leading zeros in RmCompareCompareCMP Rn, &#xO8.6;perand2NZCVUpdate CPSR flags on Rn Operand2NnegativeCMN Rn, &#xO8.6;perand2NZCVUpdate CPSR flags on Rn + Operand2NLogicalTST Rn, &#xO8.6;perand2NZCUpdate CPSR flags on Rn AND Operand2NTest equivalenceTEQ Rn, &#xO8.6;perand2NZCUpdate CPSR flags on Rn EOR Operand2AND{S} Rd, Rn, &#xOpe8;&#x.600;rand2NZCRd := Rn AND Operand2NEOR{S} Rd, Rn, &#xOpe8;&#x.600;rand2NZCRd := Rn EOR Operand2NORRORR{S} Rd, Rn, &#xOpe8;&#x.600;rand2NZCRd := Rn OR Operand2NORNT2ORN{S} Rd, Rn, &#xOpe8;&#x.600;rand2NZCRd := Rn OR NOT Operand2TBit ClearBIC{S} Rd, Rn, &#xOpe8;&#x.600;rand2NZCRd := Rn AND NOT Operand2N ARM Instruction SetQuick Reference CardSingle data item loads and storesAssemblerAction if &#xo-6.; p is LDRAct&#xop00;ion if is STRNotesLoador storeword, byteor halfwordImmediate offset&#xop00;ize}{T} Rd, [Rn {, #&#xoffs;t8.;怀}]{!}Rd := [address, size][address, size] := Rd1, NPost-indexed, immediate&#xop00;ize}{T} Rd, [Rn], &#xoffs;t00;#Rd := [address, size][address, size] := Rd2Register offset&#xop00;ize} Rd, [Rn, +/-Rm {, h&#xops8;&#x.600;}]{!}Rd := [address, size][address, size] := Rd3, NPost-indexed, register&#xop00;ize}{T} Rd, [Rn], +/-Rm {, &#xopsh;Rd := [address, size][address, size] := Rd4PC-relative&#xop00;ize} Rd, &#xlabe;&#xl000;Rd := [label, size]Not available5, NLoad or storedoublewordImmediate offset5E&#xop00;Rd1, Rd2, [Rn {, #&#xoffs;t00;]{!}Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd26, 9Post-indexed, immediate5E&#xop00;Rd1, Rd2, [Rn], #.60;offsetRd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd26, 9Register offset5E&#xop00;Rd1, Rd2, [Rn, +/-Rm {, s&#xop8.;怀h}]{!}Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd27, 9Post-indexed, register5E&#xop00;Rd1, Rd2, [Rn], +/-Rm {, &#xo8.6;psh}Rd1 := [address], Rd2 := [address + 4][address] := Rd1, [address + 4] := Rd27, 9PC-relative5E&#xop00;Rd2, &#xlabe;&#xl000;Rd1 := [label], Rd2 := [label + 4]Not available8, 9Preload data or instruction (PLD) (PLI)AssemblerAction if &#xop00;is PLDAction if &#xo-6.; p is PLINotesImmediate offset5E7&#xop00;Rn {, #&#xo8.6;ffset}]Preload [address, 32] (data)Preload [address, 32] (instruction)1, CRegister offset5E7&#xop00;Rn, +/-Rm {, &#xopsh;.60;}]Preload [address, 32] (data)Preload [address, 32] (instruction)3, CPC-relative5E7&#xop00;l.60;abelPreload [label, 32] (data)Preload [label, 32] (instruction)5, COther memory operationsAssemblerActionNotesLoad multipleBlock data loadLDM{IA|IB|DA|DB} Rn{!}, &#xregl;&#xis8.;怀t-PCLoad list of registers from [Rn]N, Ireturn (and exchange)LDM{IA|IB|DA|DB} Rn{!}, &#xregl;&#xis8.;怀t+PCLoad registers, PC := [address][31:1] ( 5T: Change to Thumb if [address][0] is 1)Iand restore CPSRLDM{IA|IB|DA|DB} Rn{!}, &#xregl;&#xis8.;怀t+PC^Load registers, branch ( 5T: and exchange), CPSR := SPSR. Exception modes only.IUser mode registersLDM{IA|IB|DA|DB} Rn, reglist-P.60;C^Load list of User mode registers from [Rn]. Privileged modes only.IPOP .60;reglistCanonical form of LDM SP!, &#xregl;&#xis8.;瀀texclusiveSemaphore operation6LDREX Rd, [Rn]Rd := [Rn], tag address as exclusive access. Outstanding tag set if not shared address.Rd, Rn not PC.Halfword or Byte6KLDREX{H|B} Rd, [Rn]Rd[15:0] := [Rn] or Rd[7:0] := [Rn], tag address as exclusive access. Outstanding tag set if not shared address. Rd, Rn not PC.Doubleword6KLDREXD Rd1, Rd2, [Rn]Rd1 := [Rn], Rd2 := [Rn+4], tag addresses as exclusive accessOutstanding tags set if not shared addresses. Rd1, Rd2, Rn not PC.Store multiplePush, or Block data storeSTM{IA|IB|DA|DB} Rn{!}, &#xregl;&#xis8.;怀tStore list of registers to [Rn]N, IUser mode registersSTM{IA|IB|DA|DB} Rn{!}, &#xregl;&#xis8.;怀t^Store list of User mode registers to [Rn]. Privileged modes only.ICanonical form of STMDB SP!, &#xregl;.60;istStoreexclusiveSemaphore operation6STREX Rd, Rm, [Rn]If allowed, [Rn] := Rm, clear exclusive tag, Rd := 0. Else Rd := 1. Rd, Rm, Rn not PC.Halfword or Byte6KSTREX{H|B} Rd, Rm, [Rn]If allowed, [Rn] := Rm[15:0] or [Rn] := Rm[7:0], clear exclusive tag, Rd := 0. Else Rd := 1Rd, Rm, Rn not PC.Doubleword6KSTREXD Rd, Rm1, Rm2, [Rn]If allowed, [Rn] := Rm1, [Rn+4] := Rm2, clear exclusive tags, Rd := 0. Else Rd := 1Rd, Rm1, Rm2, Rn not PC.Clear exclusiveClear local processor exclusive tagCNotes: availability and range of options for Load, Store, and Preload operationsNoteARM Word, B, DARM SB, H, SHARM T, BTThumb-2 Word, B, SB, H, SH, DThumb-2 T, BT, SBT, HT, SHT1offset: 4095 to +4095offset: 255 to +255Not availableoffset: 255 to +255 if writeback, 255 to +4095 otherwiseoffset: 0 to +255, writeback not allowed2offset: 4095 to +4095offset: 255 to +255offset: 4095 to +4095offset: 255 to +255Not available3Full range of {, &#xopsh;.60;}&#xopsh;{, } not allowedNot available&#xopsh;.70; restricted to LSL&#xsh00; # range 0 to 3Not available4Full range of {, &#xopsh;.60;}&#xopsh;{, } not allowedFull range of {,&#xopsh; Not availableNot available5label within +/ 4092 of current instructionNot availableNot availablelabel within +/ 4092 of current instructionNot availabl6offset: 255 to +255--offset: 1020 to +1020, must be multiple of 4.-&#xopsh;{, } not allowed--Not available-8label within +/ 252 of current instruction--Not available-9Rd1 even, and not r14, Rd2 == Rd1 + 1.--Rd1 != PC, Rd2 != PC- ARM Instruction SetQuick Reference CardARM architecture versionsCondition FieldARM architecture version and aboveMnemonicDescriptionDescription (VFP)JT or J variants of ARM architecture version and aboveEqualEqualEARM v5E, and 6 and aboveNot equalNot equal, or unorderedT2All Thumb-2 versions of ARM v6 and aboveCarry Set / Unsigned higher or sameGreater than or equal, or unordered6KARMv6K and above for ARM instructions, ARMv7 for ThumbCarry Clear / Unsigned lowerLess thanZAll Security extension versions of ARMv6 and aboveNegativeLess thanRMARMv7-R and ARMv7-M onlyPositive or zeroGreater than or equal, or unorderedXSXScale coprocessor instructionOverflowUnordered (at least one NaN operand)No overflowNot unorderedFlexible Operand 2Unsigned higherGreater than, or unorderedImmediate value#m&#xi8.6;m8mLSUnsigned lower or sameLess than or equalRegister, optionally shifted by constant (see below)Rm {, &#xopsh;}GESigned greater than or equalGreater than or equalRegister, logical shift left by registerRm, LSL RsLTSigned less thanLess than, or unorderedRegister, logical shift right by registerRm, LSR RsGTSigned greater thanGreater thanRegister, arithmetic shift right by registerRm, ASR RsLESigned less than or equalLess than or equal, or unorderedRegister, rotate right by registerRm, ROR RsALAlways (normally omitted)Always (normally omitted)All ARM instructions (except those with Note C or Note U) can have any one of these condition codes after the instruction mnemonic (that is, before the first space in the instruction as shown on this card). This condition is encoded in the instruction.All Thumb-2 instructions (except those with Note U) can have any one of these condition codes after the instruction mnemonic. This condition is encoded in a preceding IT instruction (except in the case of conditional Branch instructions). Condition codes in instructions must match those in the preceding IT instruction.On processors without Thumb-2, the only Thumb instruction that can have a condition code is B &#xlabe;.60;lRegister, optionally shifted by constant(No shift)Same as Rm, LSL #0Logical shift leftRm, LSL #.60;shiftAllowed shifts 0-31Logical shift rightRm, LSR #.60;shiftAllowed shifts 1-32Arithmetic shift rightRm, ASR #.60;shiftAllowed shifts 1-32Rotate rightRm, ROR #.60;shiftAllowed shifts 1-31Rotate right with extendRm, RRXProcessor ModesPrefixes for Parallel InstructionsUserSigned arithmetic modulo 2, sets CPSR GE bitsPSR fields(use at least one suffix)FIQ Fast InterruptSigned saturating arithmeticSuffixMeaningIRQ InterruptSigned arithmetic, halving resultsControl field mask bytePSR[7:0]SupervisorUnsigned arithmetic modulo 2, sets CPSR GE bitsFlags field mask bytePSR[31:24]AbortUnsigned saturating arithmeticStatus field mask bytePSR[23:16]UndefinedUnsigned arithmetic, halving resultsExtension field mask bytePSR[15:8]System Proprietary NoticeWords and logos marked with or are registered trademarks or trademarks owned by ARM Limited. Other brands and names mentioned herein may be the trademarks of their respective owners.Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.This reference card is intended only to assist the reader in the use of the product. ARM Ltd shallnot be liable for any loss or damage arising from the use of any information in this reference card, or any error or omission in such information, or any incorrect use of the product.Document NumberARM QRC 0001LChange LogIssueDateChangeIssueDateChangeAJune 1995First ReleaseBSept 1996Second ReleaseCNov 1998Third ReleaseDOct 1999Fourth ReleaseEOct 2000Fifth ReleaseFSept 2001Sixth ReleaseGJan 2003Seventh ReleaseHOct 2003Eighth ReleaseIDec 2004Ninth ReleaseJMay 2005RVCT 2.2 SP1KMarch 2006RVCT 3.0LMarch 2007RVCT 3.1