On Building General Modular Adders from St andard Binary Arithmetic Components Ghassem Jaberipur  Behrooz Parhami  and Saeed Nejati  Abstract We introduce an excess representation of residues for res
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On Building General Modular Adders from St andard Binary Arithmetic Components Ghassem Jaberipur Behrooz Parhami and Saeed Nejati Abstract We introduce an excess representation of residues for res

We show that our special representation leads to simp le modular arithmetic with arbitrary moduli while using standard arithmetic components such as carrysave and carrypropagate adders that have been extensi vely optimized for area power and a host

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On Building General Modular Adders from St andard Binary Arithmetic Components Ghassem Jaberipur Behrooz Parhami and Saeed Nejati Abstract We introduce an excess representation of residues for res




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Presentation on theme: "On Building General Modular Adders from St andard Binary Arithmetic Components Ghassem Jaberipur Behrooz Parhami and Saeed Nejati Abstract We introduce an excess representation of residues for res"— Presentation transcript:


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On Building General Modular Adders from St andard Binary Arithmetic Components Ghassem Jaberipur , Behrooz Parhami , and Saeed Nejati 1 Abstract We introduce an excess- representation of residues for residue number system (RNS) arithmetic, in which a flag bit selects one or the other subrange within the full range of n-bit values. We show that our special representation leads to simp le modular arithmetic with arbitrary moduli, while using standard arithmetic components such as carry-save and carry-propagate adders that have been extensi vely optimized for area, power, and a

host of other composite figures of merit. Further advantages of a unified treatment, as opposed to a multiplicity of specialized sc hemes previously proposed in connection with particular classes of moduli such as and , include simplified design process, verification, testing, and fault tolerance. Both gate-level analyses and VLSI synthesis re sults point to advantages in latency, area, and/or power compared with other proposed designs in the literature. 1. Introduction k k 2. Modulo-( ) Adders
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3. Excess- Representation Definition 1 m Table I Mod-29 addition examples ( = 5, =

3). 4. A Reconfigurable Modular Adder Table II Truth table for bits of .
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Fig. 1 Unified mod-(2 ) adder. 5. Synthesis and Comparisons Table III Area/delay evaluation of Fig. 1. Component Delay Area box CSA n KSPP Fig. 2 Ref. [2] pgh pgh n Table IV Area/delay e valuation of a KSPP adder. Component Delay Area pgh boxes n PP node XORs Total
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Table V Synthesis results. m n Design [Ref.] Delay (ns) Area (m ) Power (W) Fig. 2 Synthesis-based area comparisons. Fig. 3 Synthesis-based delay comparisons. Fig. 4 Synthesis-based power comparisons. Fig. 5 Synthesis-based

comparisons of PDP.
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6. Conclusion Acknowledgment References Residue Number Systems: Theory and Implementation IEEE Trans. Circuits and Systems I n Integration, the VLSI J. IEEE Trans. Circuits and Systems II Proc. 19th IEEE Symp. Computer Arithmetic n IET Computers & Digital Techniques n IET Circuits, Devices & Systems, IET Computers & Digital Techniques n n Proc. 14th IEEE Symp. Computer Arithmetic IEEE Trans. Circuits and Systems I n n n n IEEE Trans. Circuits and Systems I n n n IEEE Trans. Circuits and Systems I n Proc. 19th IEEE Symp. Computer Arithmetic n IEEE Trans.

Computers IEEE Trans. Computers, IEEE Trans. Computers IEEE Trans. Circuits and Systems IEEE Trans. Circuits and Systems II Proc. IEEE Intl Conf. Computer Design IEEE Trans. Computers n Proc. IEEE Symp. Computer Arithmetic IEEE Trans. VLSI Systems