Nima Aghaee Zebo Peng and Petru Eles Embedded Systems Laboratory ESLAB Linkoping University 12th Swedish SystemonChip Conference May 2013 Outline Introduction Early life failures Temperature gradient effects ID: 808908
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Temperature-Gradient Based Burn-In for 3D Stacked ICs
Nima Aghaee, Zebo Peng, and Petru ElesEmbedded Systems Laboratory (ESLAB)Linkoping University
12th Swedish System-on-Chip Conference – May 2013
Slide2Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristiconly in paper
Experimental results
May-2013
Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide3Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristicExperimental results
May-2013
Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide4Early Life May-2013
Temperature-Gradient Based Burn-In for 3D Stacked ICs4
Bathtub curve
Survival curve
Also known as
Infant mortality
Failure rate
Large
Decreasing
Failure mechanism
Birth defects
Warranty
Manufacturers warranty
Burn-in process tries to cover this area
Slide5Burn-InBurn-in is an effort to speed up the life
Elevated temperature and voltageWear mechanisms includeMetal stress voiding and electromigrationMetal sliver bridging shortsGate-oxide wearout and breakdownSome wear mechanisms strongly dependent on temperature gradients
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Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide6Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristicExperimental results
May-2013
Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide7Metal Layer Elevation
Source: T. Smorodin, J. Wilde, P. Alpern, and M. Stecher, “A temperature-gradient-induced failure mechanism in metallization under fast thermal cycling,” IEEE Transactions on Device and Materials Reliability, 2008, vol. 8, no. 3, pp. 590–599.
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Temperature-Gradient Induced Wear
Slide8Electromigration (Atomic Flux)
Migration depends on temperature gradients May-2013Temperature-Gradient Based Burn-In for 3D Stacked ICs
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J. Pak, M.
Pathak
, S. K. Lim, and D. Z. Pan, “Modeling of electromigration in through-silicon-via based 3D IC,” Electronic Components and Technology Conference (ECTC), 2011, pp. 1420–1427.
K.
Chakrabarty
, S. Deutsch, H.
Thapliyal
, and F. Ye, “TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test,” International Reliability Physics Symposium (IRPS), 2012, pp. 5F.1.1–5F.1.12.
stress
temperature
Temperature-Gradient Induced Wear
Slide9Temperature-Gradient Dependence
Creating temperature gradients during burn-in speeds up the early life more effectively than uniform heatingPotential defects are speeded up faster May-2013
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Some wear mechanisms depend on temperature gradients
Slide10Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristicExperimental results
May-2013
Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide113D Stacked IC and Burn-In
Thermal gradients for 3D-SIC 3 times larger than normal 2D ICsVery important to pay attention to temperature gradients for 3D ICsMultiple thermal maps to improve effectiveness of burn-in May-2013
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Slide12Thermal Map
For different benchmarks for a microprocessorFor different functional modes of an ICSynthetic maps to target certain defectsKnowledge from yield learning processBased on experience and empirical approachesBased on analysis and computer simulationSpecifies high and low temperature limits for each core or each thermal node
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Slide13Burn-In Moments
Wafer-Level Burn-In (WLBI)Similar to bare-die test in 2DDie-Level Burn-In (DLBI)Similar to final test in 2DUsually done after packagingPossibilities for 3DPre-bond Mid-bond
Post-bond
Final (after packaging)
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Slide14Alternatives for Creating a Thermal Map (1)
Especially for different benchmarks for a microprocessor or functional modes of an ICMight be slowMight be impossible to create large gradientsMight not be possible before final bond in 3DSome inputs are from TSVsIntermediate data usually has high volume and high speed
TSVs could not be properly accessed using test equipment
There will be a test access mechanism that has access to cores
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1. Using real inputs/input ports
Slide15Alternatives for Creating a Thermal Map (2)
Might not be achievable using real inputsMight be achievable using test access mechanismDirect access to cores May-2013
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2. Synthetic thermal maps in order to target certain defects
Slide16Description of the Problem
Multiple thermal maps are to be appliedA maps is created by selectively applying heating sequences (dummy tests)Heating sequences are applied via Test Access Mechanism (TAM)InputsThermal mapsTAM width Other IC specificationsOutput
Schedules indicating proper times for heating sequence application
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Slide17Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristicExperimental results
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Slide18Thermal Model May-2013
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Slide19Steady-State Solution for Burn-In
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Thermal model
Steady-state
Target temperatures
Slide20Necessary Reachability Condition
Stray powerStatic power (Leakage)Clock network power May-2013
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Heating sequence power
Large (largest) power
Achieved in test mode
Slide21Pulse Width Modulation - PWM
Creating arbitrary power valuesDuty cyclePeriodTest access mechanism limited bandwidth (W) May-2013
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Schedulability
condition:
Slide22Scheduling
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Slide23Ripples
On-off changes in power create ripples in temperature May-2013Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Slide24Ripples and the Period (1)
Ripples should not drive the temperature higher than or lower than limits specified in the map May-2013Temperature-Gradient Based Burn-In for 3D Stacked ICs
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Thermal model:
Power on:
Power off:
Slide25Ripples May-2013
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Slide26Ripples and the Period (2) May-2013
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Estimation of the derivative in a short time interval:
Period that temperature touches the max in an power-on period:
Smallest period (High/Low period for a core, for all cores) is the period to go with
Slide27Ripples May-2013
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Slide28Steady-State Solution - Summary
The schedule is repeated periodicallyTransition to a new thermal map is slowInitial temperatures to fade awayNew temperatures to build upSchedule generation is fastTo be faster, the transient response should be taken into account
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Slide29Outline
IntroductionEarly life failuresTemperature gradient effectsThermal mapsProposed methodsSteady state solutionTransient based heuristicExperimental results
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Slide30Experimental Setup
12 ICs1, 2, and 3 layers2 to 48 modulesMin/max in thermal maps35/4545/5555/6565/7575/85
85/95
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Slide31Experimental Results
CPU timeSteady-state solution : 2 secTransient-based heuristic : 12 minTest time percentage changeTransient-based heuristic compared with steady-state solution -78% May-2013
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Slide32Conclusion (1)
Proper temperature gradients and thermal maps should be in place during burn-inCannot be achieved using ordinary ovensUsing test access mechanism is unavoidable May-2013
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Early life failures dependency on temperature gradients
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Steady-state solution
Transient-based heuristic
Simple
Yes
No
Fast to generate the schedules
Yes
No
Fast to achieve a new thermal map
No
Yes
Supports high resolution thermal maps
No
Yes
Supports different TAM widths for different modules
No
Yes
Conclusion (2)
Slide34?
Questions