Methodology for - PowerPoint Presentation

Slide1

Methodology for Electromigration Signoff in the Presence ofAdaptive Voltage Scaling

Wei-Ting Jonas Chan

,

Andrew B. Kahng and Siddhartha

Nath

VLSI CAD LABORATORY, UC San DiegoSlide2

Outline

Motivation

Previous Work

Analysis Models

Experimental Setup and Results

ConclusionsSlide3

Bias Temperature Instability (BTI)

|

ΔV

th

| increases when device is on (stressed)

|ΔVth| is partially recovered when device is off (relaxed)

Device

aging (|

ΔVth|) accumulates over timeNBTI: PMOS PBTI: NMOS

|

V

gs

|

time

ON

OFF

ON

OFF

[VattikondaWC06]Slide4

Electromigration in Interconnects

Electromigration

(EM) is the gradual displacement of metal atoms in an interconnect

I

avg

causes

DC EM and affects power delivery networks

I

rms

causes AC EM and affects clock and logic signalsSlide5

Adaptive Voltage Scaling (AVS)Accumulated BTI

 higher

|

ΔV

th

|  slower circuitAVS can compensate for performance degradation

Circuit

Closed-loop AVS

On-chip aging monitor

Circuit performance

Voltage regulator

Circuit performance

Vdd

time

time

Without AVS

With AVS

targetSlide6

BTI + AVS Signoff

V

lib

V

BTI

Derated

library

|

V

t

|

Circuit implementation and signoff

netlist

BTI degradation and AVS

V

final

?

Step 1

Step 2

Step 3

Signoff loop of BTI

Ensure circuit meets timing requirements under BTI aging

Use AVS to offset BTI degradation Slide7

EM + BTI + AVS Signoff?

Stress

on

Wires

V

final

Design Implementation

V

lib

, V

BTI

Derated Libraries

Signoff loop of BTI + EM

Aggressive AVS scheduling results in more severe degradation

Guardband

during implementation increases due to degradation

How to signoff for EM with AVS?

What are area, power costs?

What is the impact to EM lifetime?

BTI loop

EM loopSlide8

Outline

Motivation

Previous Work

Analysis Models

Experimental Setup and Results

ConclusionsSlide9

Previous WorksEM lifetime and wire degradation modelsClosed-form lifetime models (Black, Arnaud et al.,

Federspiel

et al.)

Statistical model for wire degradation (Mishra et al.)

Claim their model reduces pessimism in Black’s Equation

EM-durable circuitsWire-sizing algorithms (Adler et al., Jiang et al.)Wire segmentation and via insertion algorithms (Li et al.)Current-aware routers (

Lienig et al., Yan et al.)BTI SignoffInteractions between AVS and BTI (Chan et al., Chen et al., Basoglu et al.)

No studies on three-way interactions between

BTI, EM and AVS!!!Slide10

Outline

Motivation

Previous Work

Analysis Models

Experimental Setup and Results

ConclusionsSlide11

EM Model:

Black’s Equation

t

50

– median time to failure (= log

e

2 x MTTF)

A* – geometry-dependent constant

J – current density in interconnect segment

n – constant ( = 2)

E

a

– activation energy of metal atoms

k – Boltzmann’s constant

T – temperature of the interconnect

EM degrades interconnect lifetime

Black’s Equation calculates lifetime

of interconnect segment due to EM degradationSlide12

New EM

Model: Mishra-

Sapatnekar

Models resistance increase due to voids in wires instead of MTTF

Derived from statistical model of nucleation and growth time

– Resistance increase due to voids in wires

– Resistivity of copper Tantalum liner

,

–

Cross section area of

of copper

and

Tantalum

liners

,

– Length of void and wire

– Diffusivity during void growth period

–

Effective

charge number

–

observation time and length of nucleation

Log-normal distributionSlide13

New EM Model: Impact on Signal Wires

Sweep different gate sizes

up to 8×

Larger

gates do not necessarily help to reduce

EM impact

∼

8% delay degradation for

buffers smaller than 4× when resistance increases to high values (∼146%)

Statistical model is optimistic in predicting delay penaltiesSlide14

New EM Model: Impact on Signal Wires

Sweep FO4

capacitive load by factors {1.0×, 1.6×, 2.1

×}

EM slows

down circuit performance

due to

increased

stage delay

increased output transition times

Delay increases by ~35% with large resistance increase ~200% Slide15

Outline

Motivation

Previous Work

Analysis Models

Experimental Setup and Results

ConclusionsSlide16

Experimental SetupMultiple implementations based on different signoff cornersAES and

DMA

designs from

Opencores

28nm foundry FDSOI technology

Commercial tool-based SP&R flowsSynopsys PrimeTime for timing analysis Matlab for AVS

simlulation with BTI and EMSlide17

AVS Signoff Corner Selection

Impl

#

1

2

3

4

5

6

7

8

V

lib

(V)

V

min

V

min

V

max

V

min

0.98V

0.97V

0.96V

0.95V

V

BTI

(V)

V

min

V

max

V

max

N/A

0.98V

0.97V

0.96V

0.95V

Characterize different derated libraries against BTI

Evaluate impact of library characterization

V

final

is predicted by cell chains ahead of implementation

Eight implementations

1

:

V

BTI

=

V

lib

=

V

min



Ignore AVS

2

:

Most pessimistic

derated

library

3

: V

BTI

=

V

lib

=

V

max



Extreme corner

for AVS

4

: No derated library (reference)

5

:

Sweep around

V

final

6

:

V

final

by cell chain prediction [ChanCK13]

7

: Sweep around

V

final

8

: Sweep around

V

finalSlide18

AVS Signoff Corner Selection

Optimistic about AVS

Pessimistic about AVSSlide19

AVS Impact on EM Lifetime

V

final

(V)

Assume

no EM fix at signoff

BTI degradation is checked at each step and MTTF is updated as

30% MTTF penalty

200mV voltage compensationSlide20

Power Penalty to Fix EM with AVS

Core power increases due to elevated voltage

P/G power increases due to both elevated voltage and mesh degradation

A tradeoff between invested guardband in signoff

Highest

invested guardband

Least

invested guardband

14% power penaltySlide21

EM Impact on AVS SchedulingAVS behavior is an important role to decide the EM penalty on lifetimeWe empirically sweep AVS voltage step size to obtain the impact

#Implementation 3 is used

AVS starts at 0.9V, and no EM fix for AVS in signoff

5 step sizes

S1 = 8mV

S2 = 10mVS3 = 15mVS4 =

18mVS5 = 20mVSlide22

EM Impact on

AVS Scheduling

1.2 years MTTF penaltySlide23

Outline

Motivation

Previous Work

Analysis Models

Experimental Setup and Results

ConclusionsSlide24

ConclusionsWe study the joint impact of BTI, AVS and

EM on signoff

We study

two

EM models and their impact on

implementation (i) Black’s Equation and (ii) Mishra-Sapatnekar

We demonstrate empirical results for lifetime, area and power penalty due to EM when AVS is involvedUp to 30% lifetime penaltyWe demonstrate empirical results for

power at different signoff cornersUp to 14% power penaltyOngoing

Improve accuracy of signoff using a temperature gradientLearning-based modeling to quantify design costs of reliabilitySlide25

Thank you!Slide26

BackupSlide27

EM Model: Mishra-Sapatnekar

Log-normal distributionSlide28

Study on EM Impact in AVS System

V

regulator

Core (V

DD

domain)

Mesh and ring

∆R

PG

(due to EM)

Assume two types of degradation

IR drop due to power mesh degradation (∆

R

PG

due

to EM)

Signal wire degradation due to EM