mini TriggerTiming Logic Unit mini TLU Introduction Status Plans Summary 21112013 David Cussans AIDA WP93 DESY 1 Introduction Provide Simple TimingSynchronisation Interface Builds on EUDET TLU ID: 477761
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Slide1
AIDA (mini) Trigger/Timing Logic Unit(mini TLU)
IntroductionStatusPlansSummary
21/11/2013
David Cussans, AIDA WP9.3, DESY
1Slide2
IntroductionProvide Simple Timing/Synchronisation Interface
Builds on EUDET TLULinked with Deliverable D8.2.2 (specification documents for the common DAQ)New for AIDA – synchronous mode ( clock/trigger/busy ) for high trigger rate
Better performance than EUDET TLUTrigger rate > 1MHz sustained , > 10MHz instantaneous
21/11/2013
David Cussans, AIDA WP9.3, DESY
2Slide3
Hardware
Implemented as FPGA Mezzanine Card (FMC).Plugs into off-the-shelf FPGA carrier Four trigger inputsSoftware adjustable thresholdThreshold and CFD
Three Device Under Test interfacesCan be fanned out to up to 30 DUT interfaces in synchronous mode with external fanout
.Open Hardware, Open Firmware: http://www.ohwr.org
/projects/
fmc-mtlu
/wiki
21/11/2013
David Cussans, AIDA WP9.3, DESY
3Slide4
Hardware
Currently only as boards bolted to plateDesign for box in progress21/11/2013
David Cussans, AIDA WP9.3, DESY
4Slide5
Hardware
LVDS TTL converters exist.This example from NIKHEF
21/11/2013
David Cussans, AIDA WP9.3, DESY
5Slide6
Development Team
21/11/2013David Cussans, AIDA WP9.3, DESY
6
David Cussans
( Bristol )
Hardware/Firmware
Francesco
Crescioli
( LPNHE )
Software
Alvaro
Dosil
(Santiago de
Compostela
)
FirmwareSlide7
TLU in actionDebugging new interface with AIDA telescopeOperation with non-AIDA telescope:
Interfacing TORCH ( LHCb upgrade proposal ) DAQ with LHCb TimePix3 telescope.Accepts clock and synchronization signals from LHCb telescope
Provides “AIDA synchronous interface” to DUT
21/11/2013
David Cussans, AIDA WP9.3, DESY
7Slide8
AIDA TLU with non-AIDA Beam-Telescope
21/11/2013
David Cussans, AIDA WP9.3, DESY
8
LHCb
Timepix3
Telescope
AIDA TLU
Telescope
Clock/Sync
FanoutSlide9
Clock/Syncronization Fanout
21/11/2013David Cussans, AIDA WP9.3, DESY
9
Up to 30 DUT
Compatible with
miniTLU
(in synchronous mode)Slide10
Status – HardwareTen AIDA miniTLU boards exist
Production organized and paid by DESYMinor hardware bugs correctable by external plug-in cable converterBug fixed design by end of AIDA21/11/2013
David Cussans, AIDA WP9.3, DESY
10Slide11
Status – Firmware
Synchronous mode implementedEUDET mode still in developmentTDC functionality tested (and works)Granularity 780psSeparate timestamp for each trigger inputBasic coincidence logic exists. Being tested and improved
21/11/2013
David Cussans, AIDA WP9.3, DESY
11Slide12
Status – SoftwareProducer for EUDAQ-2 writtenBasic Functionality Present
Sustained trigger rate of 1MHz measuredDebugging continues21/11/2013
David Cussans, AIDA WP9.3, DESY
12Slide13
PlansCurrent team available until end March 2105Aim to have “finished” TLU by then.
Longer term plans depend on outcome of AIDA-2020If no AIDA-2020 support on best-efforts basisHardware, Firmware, Software all freely available( Modifying PCB needs access to CERN CAD libraries )
21/11/2013
David Cussans, AIDA WP9.3, DESY
13Slide14
SummaryAim: Simple hardware unit to make common beam-tests easier.Basic functionality achieved
Full functionality badly delayed but nearing completionExisting TLU specification document will be uploaded as an AIDA note.
21/11/2013
David Cussans, AIDA WP9.3, DESY
14