EE194 Joel Grodstein - PowerPoint Presentation

EE194 Joel Grodstein EE 194: Advanced VLSI Spring 2018 Tufts University Instructor: Joel Grodstein joel.grodstein@tufts.edu Course introduction

LogisticsClass web page: http://www.ee.tufts.edu/ee/194VLSEE194 Joel Grodstein

PrerequisitesVLSI:Basic digital design (gates, flip flops, Boolean algebra)Basic idea of finite state machinesEE 103 or equivalentBasic architectureComputer scienceOne of your homeworks will be writing a computer program in C or C++. Nothing fancy, but you have to be able to get code written & workingEE194 Joel Grodstein

What is this class about?First time this class is offeredSmall class means we can be flexible in tailoring it to students' interests.A few topics we'll definitely cover, and several more that we may or may not. We may add others on request.The pace will be whatever is needed so that the large majority of people understand most everything.EE194 Joel Grodstein

ProfessorJoel GrodsteinHalf-time lecturer at Tufts (in my 2nd semester)25 years of experience in VLSI (retired) at Intel, HP, Compaq, Digital Equipment, Evans & Sutherlandjoel.grodstein@tufts.eduOffice Halligan extension #11Office hours 1 hour before class. Other times by arrangement.Feel free to use the office hours, even just to chat about the computer industry.

The semester in detailHere's our detailed list of potential topicsEE194 Joel Grodstein

Process scalingProcess scaling has been the engine driving the computing industry for many yearsThat era is endingWhat was scaling, and why is it ending?How does scaling affect power? Speed?Old prediction: chips would turn into nuclear reactors; did not come true . Why not?EE194 Joel Grodstein

Static timing analysisWhat is it?Given a collection of gates, each with a delay (but paying little or no attention to logic function)Usually no input pattern given (hence "static")Predict worst-case timing on every node & see if the chip will operate at frequencyWe will:Understand the basics of gate delay & why it can be hard to predictUnderstand timing constraints for flops and latchesUnderstand the basics of speed binning, and its interaction with STAManufacturing is cool – because money is cool For those who went through the STA lectures in last spring’s CAD class, we’ll go deeper this timeEE194 Joel Grodstein

ClockingUnderstand conditional clocks:usage for power savings and for functionalityelectrical implementationstatic-timing analysis constraints for conditional clocksClock distributionSending one signal to a billion destinations is really hardWhile minimizing power, skew, jitter, …We’ll learn various distribution strategiesAnd clock islands and ways to cross themFor those who went through the STA lectures in last spring’s CAD class, we’ll go deeper this timeEE194 Joel Grodstein

ValidationHow do you know if your Verilog design is correct?Lots of validationUsually not covered well in university coursesNot thought of as glamorous enoughBut validation is where the most jobs areAnd some would argue it’s more fun than designMay bring in a guest speaker from Cavium/MarvellEE194 Joel Grodstein

DVFSDiscrete Voltage and Frequency Switching Used by most processors nowadays, to save powerTo not have your chip be a nuclear reactorWe’ll cover the power savingsThe effect on STAThe effect on speed binningThe effect on clock islandsPhysical issues in delivering lots of variable voltages to a dieEE194 Joel Grodstein

Latching and scanWe need tests for chips with 10M gates.Any transistor or wire can be broken. How do you write the tests to test so many things?And your test set should be reasonably minimalLearn about scan and ATPG, and how they affect flop designEE194 Joel Grodstein

VLSI futuresWhere will VLSI be in 10-20 years?Learn about a few interesting possible futuresDark silicon & heterogeneous processorsTimed digital logicStochastic digital logicReprogramming bacteria to computeEE194 Joel Grodstein

For each major topic…2-4 lectures covering the topic in a "reasonable" amount of detail (nowhere near exhaustive)Assignments:Most unit has a set of homework problems; one or two of these should be replace by a one-on-one oral quiz. Some have extra-credit problem(s) as wellThe STA unit also has a computer programTwo of the units have a research paper that we’ll discuss in classNo midterm or final exam currently plannedEE194 Joel Grodstein

What other topics would be nice?EE194 Joel Grodstein

LogisticsNo book… just foils, notes & the research papersI usually teach on Powerpoint slides (like this one...)Tools:Hand in HW via Provide.Get grades back via Trunk.E-mail to joel.grodstein@tufts.edu for other questions.EE194 Joel Grodstein