Jim Seton May 2016 1 3 Must cycle FPGA power before starting 4 Set EVM Clocking Mode to Onboard 5 Set DAC Data Input Rate to 73728 6 Set Number of SerDes Lanes to 8 ID: 641733
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DAC38J84 EVM Quick Start Guide
Jim SetonMay, 2016
1Slide2
3. Must cycle FPGA power before starting
4. Set EVM Clocking Mode to “Onboard”5. Set DAC Data Input Rate to “737.28”6. Set Number of SerDes Lanes to “8”7. Set Interpolation to “1”
GUI shall look as shown belowSlide3
3. Set clk0 to div by 8
4. Set clk12 to div 16Slide4
Loaded 10MHz tone DAC Test Pattern
4Slide5
The VC707 status LED’s shall look as follows:
D1 – BlinkingD2 – Blinking
D3 – Blinking
D4 – on
D5 – off
D6 – off
D7 – off
D8 – on
5Slide6
Go back to the DAC38J8x GUI
1. Click on button 2 called “Reset DAC JESD Core”2. Click on button 3 called “Trigger LMK04828 SYSREF”Slide7
Alarm statusSlide8
JESD Block